ZL30106QDG Zarlink, ZL30106QDG Datasheet - Page 28

• Manufacturer Part Number: ZL30106QDG
• Description: SONET/SDH/PDH Network Interface 64-Pin TQFP
• Manufacturer: Zarlink

Specifications of ZL30106QDG

• Package: 64TQFP
• Power Supply Type: Analog
• Typical Supply Current: 68(Max) mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.62 V
• Maximum Operating Supply Voltage: 3.63 V

4.6
The ZL30106 can lock directly to a 2 kHz reference or an 8 kHz reference, but the low frequency of these
references restricts the value of the highest loop filter that can be used. The clock-and-sync pair synchronization
technique enables the ZL30106 to align its output 2 kHz and 8 kHz frame pulses with 2 kHz and 8 kHz references
without restricting the loop filter. Therefore the output clocks and frame pulses will track the input clock and frame
pulse pair closely even in the presence of jitter on the reference input.
The clock-and-sync pair mechanism is enabled as soon as a valid 2 kHz or 8 kHz frame pulse is detected on the
REF_SYNC input. The REF_SYNC pulse must be generated from the clock that is present on the REF input. The
ZL30106 checks the number of REF cycles in the REF_SYNC period. If this is not the nominal number of cycles,
the REF_SYNC pulse is considered invalid. For example, if REF is a 8.192 MHz clock then there must be exactly
1024 REF cycles in a REF_SYNC period. If a valid REF_SYNC pulse is detected, the ZL30106 will align the rising
edges of the REF clock and the corresponding output clock such that the rising edge of the F2ko or F8o/F32o
output frame pulse is aligned with the frame boundary indicated by the REF_SYNC signal. The rising edges of the
REF and the corresponding output clock that are aligned, are the ones that lag the rising edges of the REF_SYNC
and the F8o pulses respectively. This is illustrated in Figure 18. If an ST_BUS clock and frame pulse pair is used as
the REF and REF_SYNC inputs, the ST-BUS frame pulse must be inverted first before it can be used as the
REF_SYNC pulse.
Clock-and-Sync Pair Synchronization
REF0
REF_OOR0
(internal signal)
REF_FAIL0
HOLDOVER
REF_SEL
LOCK
Note: This scenario is based on REF1 remaining good throughout the duration.
LOCK pin behaviour depends on phase and frequency offset of REF1.
Figure 17 - Automatic Reference Switching - Out-of-Range Reference Failure
Frequency Precision failure
10 to 20 s
REF0
REF1
Zarlink Semiconductor Inc.
ZL30106
28
Lock Time
Data Sheet