ADQ112 Sp Devices, Inc., ADQ112 Datasheet - Page 4

• Manufacturer Part Number: ADQ112
• Description: High Speed Digitizer
• Manufacturer: Sp Devices, Inc.

Specifications of ADQ112

• Transmission Media Type: Cable
• Power Supply Type: Analog
• Typical Operating Supply Voltage: 12 V

3
Exposure to conditions exceeding these rating
may reduce life time or permanently damage the
device.
The ADQ112 has a built in fan to cool the device.
If the air flow is blocked or the fan malfunctions,
the temperature surveillance unit will protect the
ADQ112 from overheating by shutting down parts
of the device.
The SMA connectors have an expected life time of
500 operations. For frequent connecting and dis-
connecting of cables, connector savers are rec-
ommended.
4
4.1
Figure 4: Block diagram
4.2
The analog input is single ended AC coupled 50
ohm. The single ended signal is converted to a dif-
ferential signal in a balun.
4.3
The ADC configuration is two 12 bit 550MSps
ADCs which are time interleaved to reach
1.1 GSps effective sampling rate. The time inter-
Document Number
08-0132
Revision
C
ABSOLUTE MAXIMUM RATINGS
Supply voltage (to GND)
Analog input (AC)
Trigger input (to GND)
Clock input (AC)
Ambient temperature
(operation)
Clk/Ref
Analog
Trig
GPIO
Absolute Maximum ratings
Architecture
Overview
Analog Front End, AFE
ADC
Clock
mgmt
ADC
Virtex5 SX50T
Int Ref
X-tal
FPGA#1
Algorithm
Date
2009-12-21
Printed
2009-12-22
Min
Virtex 5 LX30T
Communication
–0.4 V
FPGA#2
DRAM
–3 V
0
o
C
Max
4.4 V
3.3 V
cPCIe
PXIe
USB
45
2.0
3.7 V
Contact
Signal Processing Devices Sweden AB
Teknikringen 6, SE-583 33 Linköping, SWEDEN
www.spdevices.com
14 V
o
PP
PP
C
leaving is enabled by SP Devices’ time interleav-
ing algorithm ADX216.
4.4
The clock generator consists of a crystal oscillator
as a clock reference and a PLL with built in VCO.
The PLL has also built in dividers for generating
necessary clock frequencies on the board. The
sampling frequency is set by configuring these fre-
quency dividers.
There is also an external SMA connector for either
an external clock reference or an external clock
source.
4.5
The data outputs of the ADCs are connected to a
first Xilinx XC5VSX50T-3 FPGA which runs the
time interleaving algorithm ADX216. The data is
then transferred to a second FPGA, Xilinx
XC5VLX30T-1, which handles the communication
with the host and the batch data RAM. This FPGA
is open for user applications through the ADQ
Development Kit. 29 DSP elements and 30 % of
the logic is available for user applications.
4.6
There is 170 MSamples data batch memory. The
data batch length for each recording is set to any
value within this range. For more information
about memory handling, see
4.7
The ADQ112 is connected to the host computer
through a Hi-Speed USB interface which is used
for control and uploading of data.
The USB connection can be configured in a
streaming mode. The sustained data rate is then
25 MBytes/s
a data reduction algorithm, implemented through
the ADQ Development Kit.
See
(cPCIe) / PXI Express (PXIe) interface.
4.8
4.8.1
The ADQ112 has several trigger options
•
•
1. This is highly dependent of other tasks performed by
the operating system on the host computer.
Software trigger
Level trigger
Section 6.1
Clock
FPGAs
Memory
Interface
Trigger
Overview
1
. This is typically used together with
for Compact PCI Express
Section
ADQ112
Datasheet
4.8.
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