ZL30407QCG1 Zarlink, ZL30407QCG1 Datasheet - Page 23

• Manufacturer Part Number: ZL30407QCG1
• Description: PB FREE SONET/SDH NETWORK ELEMENT PLL
• Manufacturer: Zarlink

FCS pin: Filter Characteristic Select. The FCS (pin 9) input is used to select the filtering characteristics of the
Core PLL. See Table 1, “Loop Filter Selection” on page 13 for details.
RefSel: Reference Source Select. The RefSel (pin 47) input selects the PRI (primary) or SEC (secondary) input
as the reference clock for the Core PLL. The logic level at this input is sampled by the rising edge of F8o.
RefAlign: Reference Alignment. The RefAlign (pin 48) input controls phase realignment between the input
reference and the generated output clocks.
4.1.2
The ZL30407 has four dedicated status pins for indicating modes of operation and quality of the Primary and
Secondary reference clocks. These pins are listed below:
LOCK - This output goes high after the ZL30407 has completed its locking sequence (see section 2.2.3 for details).
HOLDOVER - This output goes high when the Core PLL enters Holdover mode. The Core PLL will switch to
Holdover mode if the respective Acquisition PLL enters Holdover mode or if the mode select pins or bits are set to
Holdover (MS2, MS1 = 01).
PRIOR - This output goes high when the primary reference frequency deviates from the PLL center frequency by
more than ±12 ppm. See PRIOR pin description for details.
SECOR - This output goes high when the secondary reference frequency deviates from the PLL center frequency
by more than ±12 ppm. See SECOR pin description for details.
4.2
Software control is enabled by setting the HW pin to logic zero (HW = 0). In this mode all hardware control pins
(inputs) are disabled and all status pins remain enabled. The ZL30407 has a number of registers that provide all the
functionality available in Hardware control and in addition they offer advanced control and monitoring that is only
available in Software control (see Figure 7 "Hardware and Software Control Options").
4.2.1
The ZL30407 has a number of registers that provide greater operational flexibility than available pins in Hardware
control (see Figure 7 "Hardware and Software Control Options"). The MS2, MS1, FCS2, FCS, RefSel and RefAlign
bits perform the same function as the corresponding pins. Two additional bits AHRD and MHR support recovery
from Auto Holdover mode and they are described in section 3.2.4.
Software Control
Status Pins
Control Bits
RefSel
FCS
0
1
0
1
Filter corner frequency set to 1.5 Hz
Filter corner frequency set to 0.1 Hz
Core PLL connected to the Primary Acquisition PLL
Core PLL connected to the Secondary Acquisition PLL
Table 3 - Filter Characteristic Selection
Table 4 - Reference Source Select
Zarlink Semiconductor Inc.
ZL30407
Filtering Characteristic
Input Reference
23
Data Sheet