ZL30106QDG1 Zarlink, ZL30106QDG1 Datasheet - Page 22

• Manufacturer Part Number: ZL30106QDG1
• Description: SONET/SDH/PDH Network Interface 64-Pin TQFP
• Manufacturer: Zarlink

Specifications of ZL30106QDG1

• Package: 64TQFP
• Power Supply Type: Analog
• Typical Supply Current: 68(Max) mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.62 V
• Maximum Operating Supply Voltage: 3.63 V

4.3
The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which
are synchronized to one of three reference inputs (REF0, REF1 or REF2). These signals are available in two
groups controlled by the OUT_SEL2:0 pins, see Table 3.
4.4
The ZL30106 has three possible manual modes of operation; Normal, Holdover and Freerun. These modes are
selected with mode select pins MODE_SEL1 and MODE_SEL0 as is shown in Table 4. Transitioning from one
mode to the other is controlled by an external controller. The ZL30106 can be configured to automatically select a
valid input reference under control of its internal state machine by setting MODE_SEL1:0 = 11. In this mode of
operation, a state machine controls selection of references (REF0 or REF1) used for synchronization.
4.4.1
Freerun mode is typically used when an independent clock source is required or immediately following system
power-up before network synchronization is achieved.
In Freerun mode, the ZL30106 provides timing and synchronization signals which are based on the master clock
frequency (supplied to OSCi pin) only and are not synchronized to the reference input signals.
The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a
is required, the master clock must also be
Output Clock and Frame Pulse Selection
Modes of Operation
Freerun Mode
OUT_SEL1:0
OUT_SEL2
MODE_SEL1
00
01
10
11
0
1
0
0
1
1
Table 3 - Clock and Frame Pulse Selection with OUT_SEL Pin
MODE_SEL0
C2o, C16o, C32, C65o
C2o, C4o, C8o, C16o
0
1
0
1
Generated Clocks
±
Table 4 - Operating Modes
32 ppm. See Applications - Section 6.2, “Master Clock“.
Zarlink Semiconductor Inc.
C8.4o
C34o
C44o
C6o
ZL30106
22
(Normal with automatic Holdover and
Normal (with automatic Holdover)
automatic reference switching)
Automatic
Holdover
Freerun
Mode
Generated Frame Pulses
F16o, F32o, F65o
F4o, F8o, F16o
±
32 ppm output clock
Data Sheet