MT8967AS1 Zarlink, MT8967AS1 Datasheet - Page 11

• Manufacturer Part Number: MT8967AS1
• Description: Audio Codec 1ADC / 1DAC 8-Bit 20-Pin SOIC W Tube
• Manufacturer: Zarlink
• Type: PCMr

Specifications of MT8967AS1

• Package: 20SOIC W
• Adc/dac Resolution: 8 Bit
• Number Of Channels: 1ADC /1 DAC
• Number Of Adc Inputs: 2
• Number Of Dacs: 1
• Operating Supply Voltage: ±5 V

Powerdown
Powerdown of the chip is achieved in several ways:
Internal Control:
1)
2)
External Control:
1)
2)
0
1
1
BITS 0-2
during this period the chip will accept input only from C2i. The B-register is reset to zero forcing SD0-5 to
be inactive. Bits 0-5 of Register A (gain adjust bits) are forced to zero and bits 6 and 7 of Register A
become logic high thus reinforcing the powerdown.
this condition the chip will be in the same state as in (1) above.
Note: If C2i stops at a continuous logic low (GNDD), the digital data and status is indeterminate.
receives its control word input via CSTi, when F1i is low and CA input is either at V
removed from the filters and analog sections of the chip. The analog output buffer at V
to GNDA. DSTo becomes high impedance and the clocks to the majority of the logic are stopped. SD
outputs are unaffected and may be updated as normal.
described in External Control (1) above.
Initial Power-up. Initial application of V
Loss of C2i. Powerdown is entered 10 to 40 µs after C2i has assumed a continuous logic high (V
Register A. Powerdown is controlled by bits 6 and 7 (when both at logic high) of Register A which in turn
CSTi Input. With CA at V
1
0
1
Transmit filter testing, i.e.:
Receive filter testing, i.e.:
Codec testing i.e.:
Transmit filter input connected to V
Receive filter and Buffer disconnected from V
Receive filter input connected to V
Receive filter input disconnected from codec
Codec analog input connected to V
Codec analog input disconnected from transmit filter output
Codec analog output connected to V
V
R
disconnected from receive filter output
EE
and CSTi held at continuous logic high the chip assumes the same state as
MT8960/61/62/63/64/65/66/67
Table 3 - Control States - Register B
LOGIC CONTROL OUTPUTS SD
DD
Zarlink Semiconductor Inc.
and V
EE
11
X
X
X
input
causes powerdown for a period of 25 clock cycles and
input
R
R
0
-SD
2
EE
or GNDD. Power is
R
will be connected
Data Sheet
DD
). In