MT8963AE1 Zarlink, MT8963AE1 Datasheet - Page 6

• Manufacturer Part Number: MT8963AE1
• Description: Audio Codec 1ADC / 1DAC 8-Bit 20-Pin PDIP Tube
• Manufacturer: Zarlink
• Type: PCMr

Specifications of MT8963AE1

• Package: 20PDIP
• Adc/dac Resolution: 8 Bit
• Number Of Channels: 1ADC /1 DAC
• Number Of Adc Inputs: 2
• Number Of Dacs: 1
• Operating Supply Voltage: ±5 V

V
where C = chord number (0-7)
V
The recommended reference voltage for the MT8960 series of codecs is 2.5 V ±0.5%. The output voltage from the
reference source should have a maximum temperature coefficient of 100 ppm/C°. This voltage should have a total
regulation tolerance of ±0.5% both for changes in the input voltage and output loading of the voltage reference
source. A voltage reference circuit capable of meeting these specifications is shown in Figure 5. Analog
Devices’AD1403A voltage reference circuit is capable of driving a large number of codecs due to the high input
impedance of the V
to this pin. A 0.1 µF capacitor connected from V
recommended to minimize noise entering through V
characteristics.
Timing
The codec operates in a synchronous manner (see Figure 9a). The codec is activated on the first positive edge of
C2i after F1i has gone low. The digital output at DSTo (which is a three-state output driver) will then change from
a high impedance state to the sign bit of the encoded PCM word to be output. This will remain valid until the next
positive edge, when the next most significant bit will be output.
On the first negative clock edge (after F1i signal has been internally synchronized and CA is at GNDD or V
logic signal present at DSTi will be clocked into the input shift register as the sign bit of the incoming PCM word.
The eight-bit word is thus input at DSTi on negative edges of C2i and output at DSTo on positive edges of C2i.
F1i must
preventing further input data to DSTi. F1i will continue to be sampled on every positive edge of C2i. (Note: F1i may
subsequently be taken low during the same sampling frame to enable entry of serial data into CSTi. This occurs
usually mid-frame, in conjunction with CA=V
PCM input and output are inhibited by CA at V
Internally the codec will then perform a decode cycle on the newly input PCM word. The sampled and held analog
signal thus decoded will be updated 25 µs from the start of the cycle. After this the analog input from the filter is
sampled for 18 µs, after which digital conversion takes place during the remaining 82 µs of the sampling cycle.
Ref
Ref
is a high impedance input with a varying capacitive load of up to 40 pF.
X
S = step number (0-15)
[(
return
+5 V
128
2
C
)(
Ref
to
16.5 + S
input. Normal precautions should be taken in PCB layout design to minimize noise coupling
a high
32
NC
8
1
)]
AD1403A
NC
7
2
2.5 V
level after
± V
Figure 5 - Typical Voltage Reference Circuit
MT8960/61/62/63/64/65/66/67
NC
6
3
OFFSET
NC
NC
5
4
C≠0
DD
DD
Zarlink Semiconductor Inc.
the eighth clock pulse causing DSTo to enter high impedance and
, in order to enter an 8-bit control word into Register B. In this case,
.)
Ref
to ground and located as close as possible to the codec is
6
Ref
. This capacitor should have good high frequency
0.1 µF
V
Ref
FILTER/CODEC
MT8960-67
Data Sheet
EE
) the