AD1835AASZ Analog Devices Inc, AD1835AASZ Datasheet - Page 16

• Manufacturer Part Number: AD1835AASZ
• Description: Audio Codec 2ADC / 8DAC 24-Bit 52-Pin MQFP
• Manufacturer: Analog Devices Inc
• Type: General Purposer

Specifications of AD1835AASZ

• Package: 52MQFP
• Adc/dac Resolution: 24 Bit
• Number Of Channels: 2ADC /8 DAC
• Sampling Rate: 96 KSPS
• Number Of Adcs: 2
• Number Of Dacs: 8
• Operating Supply Voltage: 3.3|5 V
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 105 / 108
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-BQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD1835AEB - BOARD EVALUATION FOR AD1835A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1835A
Pin Name
ASDATA (O)
DSDATA1 (I)
DSDATA2 (I)/AAUXDATA1 (I)
DSDATA3 (I)/AAUXDATA2 (I)
DSDATA4 (I)/AAUXDATA3 (I)
ALRCLK (O)
ABCLK (O)
DLRCLK (I)/AUXLRCLK(I/O)
DBCLK (I)/AUXBCLK(I/O)
(FROM AUX ADC No. 1)
(FROM AUX ADC No. 1)
(FROM AUX ADC No. 2)
(FROM AUX ADC No. 1)
(FROM AUX ADC No. 3)
AAUXDATA1 (IN)
AAUXDATA2 (IN)
AAUXDATA3 (IN)
TDM (OUT)
LRCLK I
DSDATA1
ASDATA1
DSDATA1
BCLK I
TDM (IN)
ASDATA
FSTDM
BCLK
TDM
AUX
AUX
2
2
S
S
AUX BCLK FREQUENCY IS 64
MSB TDM
MSB TDM
1ST
1ST
CH
CH
INTERNAL
INTERNAL
ADC L1
DAC L1
32
32
I
I
I
I
I
I
LRCLK for ADC
BCLK for ADC
LRCLK In/Out Internal DACs
BCLK In/Out Internal DACs
2
2
2
2
2
2
S Mode
S Data Out, Internal ADC
S Data In, Internal DAC1
S Data In, Internal DAC2
S Data In, Internal DAC3
S Data In, Internal DAC4
Table IV. Pin Function Changes in Auxiliary Mode
AUX_ADC L2
INTERNAL
DAC L2
I
I
I
2
2
2
S – MSB LEFT
S – MSB LEFT
S – MSB LEFT
Figure 13. Auxiliary Mode Timing
FRAME RATE; TDM BCLK FREQUENCY IS 256
LEFT
AUX_ADC L3
INTERNAL
DAC L3
–16–
AUX_ADC L4
INTERNAL
DAC L4
Auxiliary Mode
TDM Data Out to SHARC.
TDM Data In from SHARC.
AUX-I
AUX-I
AUX-I
TDM Frame Sync Out to SHARC (FSTDM).
TDM BCLK Out to SHARC.
AUX LRCLK In/Out. Driven by external LRCLK from ADC in
slave mode. In master mode, driven by MCLK/512.
AUX BCLK In/Out. Driven by external BCLK from ADC
in slave mode. In master mode, driven by MCLK/8.
INTERNAL
INTERNAL
ADC R1
DAC R1
2
2
2
S Data In 1 (from External ADC).
S Data In 2 (from External ADC).
S Data In 3 (from External ADC).
FRAME RATE.
AUX_ADC R2
INTERNAL
DAC R2
AUX_ADC R3
INTERNAL
DAC R3
RIGHT
I
I
I
2
2
2
S – MSB RIGHT
S – MSB RIGHT
S – MSB RIGHT
AUX_ADC R4
MSB TDM
MSB TDM
INTERNAL
DAC R4
8TH
8TH
CH
CH
REV. A