92HD89B2X5NDGXZBX Integrated Device Technology (Idt), 92HD89B2X5NDGXZBX Datasheet - Page 29

• Manufacturer Part Number: 92HD89B2X5NDGXZBX
• Description: Audio Codec 2ADC / 2DAC 24-Bit 40-Pin VFQFPN Tray
• Manufacturer: Integrated Device Technology (Idt)
• Type: PCMr

Specifications of 92HD89B2X5NDGXZBX

• Package: 40VFQFPN
• Adc/dac Resolution: 24 Bit
• Number Of Channels: 2ADC /2 DAC
• Sampling Rate: 192 KSPS
• Number Of Adc Inputs: 10
• Number Of Dac Outputs: 11
• Number Of Dacs: 2
• Operating Supply Voltage: 1.5|3.3|5 V

92HD89B
Four channel HD Audio codec optimized for low power
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
2.15. Digital PC-Beep
2.16. Headphone Drivers
2.17. EAPD
Bit_Clk
Reset#
This block uses an 8-bit divider value to generate the PC beep from the 48kHz HD Audio Sync
pulse. The digital PC_Beep block generates the beep tone on all Pin Complexes that are currently
configured as outputs. The HD Audio spec states that the beep tone frequency = (48kHz HD Audio
SYNC rate) / (4*Divider), producing tones from 47 Hz to 12 kHz (logarithmic scale). Other audio
sources are disabled when digital PC_Beep is active.
It should be noted that digital PC Beep is disabled if the divider = 00h.
PC-Beep may be attenuated and distorted when the CODEC is in D3 depending on the load imped-
ance seen by the output amplifier since all ports are in a low power state while in D3. Load imped-
ances of 10K or larger can support full scale outputs but lower impedance loads will distort unless
the output amplitude is reduced. Digital PC_Beep requires a clock to operate and the CODEC will
prevent the system from stopping the bus clock while in D3 by setting the Clock_Stop_OK bit to 0 to
indicate that the part requires a clock.
The codec implements headphone capable outputs on some ports. The Microsoft Windows Logo
Program allows up to the equivalent of 100ohms in series. However, an output level of +3dBV at the
pin is required to support 300mV at the jack with a 32ohm load and 1V with a 320 ohm load. Micro-
soft allows device and system manufactures to limit output voltages to address EU safety require-
ments. (WLP 3.09 - please refer to the latest Windows Logo Program requirements from Microsoft.)
Power limiting may be implemented through the use of an external series resistance.
The EAPD pin also supports SPDIF_OUT and GPIO functions. The pin defaults to EAPD after power
on reset and will remain in EAPD mode until either GPIO is enabled for pin 47 or the port is enabled
as an output to support SPDIF_OUT. Although named External Amplifier Power Down (EAPD) by
the HD Audio specification, this pin operates as an external amplifier power up signal. The EAPD
Beep enabled by
Driver
Analog PC_Beep Behavior – D3 clockless
Bus Driver sets
controller to D3
due to inactivity
Vista or Linux
29
Beep Enabled
Bus Driver sets
controller to D0
V 1.0 11/10
92HD89B