MT88E46ASR1 Zarlink, MT88E46ASR1 Datasheet - Page 3

• Manufacturer Part Number: MT88E46ASR1
• Description: Caller ID CMOS 3.58MHz 3.3V/5V 20-Pin SOIC T/R
• Manufacturer: Zarlink

Specifications of MT88E46ASR1

• Package: 20SOIC
• Telecommunication Standards Supported: Bellcore GR-30-CORE|SR-TSV-002476|TIA/EIA-716|TIA/EIA-777
• Fabrication Technology: CMOS
• Maximum Data Rate: 1.212 KBd
• Typical Operating Supply Voltage: 3.3|5 V
• Typical Supply Current: 4.3 mA
• Operating Frequency: 3.58 MHz

Pin Description
Data Sheet
Pin #
10
11
12
13
14
15
16
17
18
19
20
9
DR/DET
DCLK
DATA
Name
IN2+
CB1
CB2
IN2-
Vdd
GS2
NC
CD
IC
3-Wire FSK Interface Data Clock (Schmitt Logic Input/CMOS Logic Output). In interface mode 0
(when the CB0 pin is logic low) this is a CMOS output whose rising edge denotes the nominal mid-point
of a bit in the FSK data byte.
In interface mode 1 (when the CB0 pin is logic high) this is a Schmitt trigger input used to shift the FSK
data byte out of an on chip buffer to the DATA pin.
3-Wire FSK Interface Data (CMOS Logic Output). Mark frequency corresponds to logical 1. Space
frequency corresponds to logical 0.
In interface mode 0 (when the CB0 pin is logic low) the FSK serial bit stream is output to DATA directly.
In interface mode 1 (when the CB0 pin is logic high) the start bit is stripped off, the data byte and the
trailing stop bit are stored in a 9 bit buffer. At the end of each word indicated by the DR signal at the DR/
DET pin, the microcontroller should shift the byte out to DATA by applying 8 read pulses to the DCLK
pin. A 9th DCLK pulse will shift out the trailing stop bit for framing error checking.
3-Wire FSK Interface Data Ready/CAS Detect (CMOS Logic Output). Active low.
This is a dual purpose pin which indicates the end of an FSK word or the end of CAS.
Data Ready: When FSK demodulation is enabled this pin denotes the end of a word. In both FSK
interface modes 0 and 1, it is normally high and goes low for half a bit time at the end of a word. In mode
1 if DCLK starts while DR is low, the first rising edge of the DCLK input will return DR to high. This
feature allows an interrupt requested by a low going DR to be cleared upon reading the first DATA bit.
CAS Detect: When CAS detection is enabled, this pin goes low after the end of CAS for 416 µs
(nominal) to indicate that CAS has been detected.
Internal Connection. Must be left open circuit.
No Connection. This pin is not bonded to the die and is unaffected by external connections.
Carrier Detect (CMOS Logic Output). Active low.
A logic low indicates that an FSK signal is present. A 10 ms time hysteresis has been provided to allow
for momentary signal discontinuity. The demodulated FSK data is ignored until carrier detect has been
activated.
Positive Power Supply. A decoupling capacitor should be connected directly across the Vdd and Vss
pins.
Control Bit 1 (CMOS Logic Input). Together with CB2 this pin enables FSK demodulation or CAS
detection. See Tables 1 and 2.
Control Bit 2 (CMOS Logic Input). Together with CB1 this pin enables FSK demodulation or CAS
detection. See Tables 1 and 2.
Gain Select 2 (Output). This is the output of the GS2 op-amp. The op-amp should be used to connect the
MT88E46 to the receive pair of the telephone hybrid or speech IC. The signal can be amplified or
attenuated at GS2 via selection of the feedback resistor between GS2 and IN2-.
When the application is a telephone adjunct box where there is no hybrid or speech IC, if the GS2 gain
with respect to Tip/Ring is to be set to the same as that of GS1, the GS2 op-amp can be connected as a
voltage follower to the GS1 op-amp output (see Figure 5).
The GS2 signal is used for ‘off hook mode’ CAS detection only as selected via the CB1 and CB2 pins.
See Tables 1 and 2.
GS2 Op-Amp Inverting Input. The op-amp is for connecting the MT88E46 to the receive pair of the
telephone hybrid or speech IC.
GS2 Op-Amp Non-Inverting Input. The op-amp is for connecting the MT88E46 to the receive pair of
the telephone hybrid or speech IC.
Description
MT88E46
3