NTD50N03R-35G ON Semiconductor, NTD50N03R-35G Datasheet

MOSFET N-CH 25V 7.8A IPAK

NTD50N03R-35G

Manufacturer Part Number
NTD50N03R-35G
Description
MOSFET N-CH 25V 7.8A IPAK
Manufacturer
ON Semiconductor
Datasheet

Specifications of NTD50N03R-35G

Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
12 mOhm @ 30A, 11.5V
Drain To Source Voltage (vdss)
25V
Current - Continuous Drain (id) @ 25° C
7.8A
Vgs(th) (max) @ Id
2V @ 250µA
Gate Charge (qg) @ Vgs
15nC @ 11.5V
Input Capacitance (ciss) @ Vds
750pF @ 12V
Power - Max
1.5W
Mounting Type
Through Hole
Package / Case
IPak, TO-251, DPak (3 straight short leads + tab)
Configuration
Single
Transistor Polarity
N-Channel
Resistance Drain-source Rds (on)
0.019 Ohms
Forward Transconductance Gfs (max / Min)
15 S
Drain-source Breakdown Voltage
25 V
Gate-source Breakdown Voltage
+/- 20 V
Continuous Drain Current
45 A
Power Dissipation
50 W
Maximum Operating Temperature
+ 175 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
NTD50N03R
Power MOSFET
25 V, 45 A, Single N−Channel, DPAK
Features
Applications
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 4
Continuous Drain
Current (R
(Note 1)
Power Dissipation
(R
Continuous Drain
Current (R
(Note 2)
Power Dissipation
(R
Continuous Drain
Current (R
(Note 1)
Power Dissipation
(R
Pulsed Drain Current
Current Limited by
Package
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Drain−to−Source (dv/dt)
Single Pulse Drain−to−Source Avalanche
Energy (T
I
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
L
Drain−to−Source Voltage
Gate−to−Source Voltage
Planar Technology
Low R
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
Pb−Free Packages are Available
VCORE DC−DC Buck Converter Applications
Optimized for High Side Switching
qJA
qJA
qJC
= 6.32 A
) (Note 1)
) (Note 2)
) (Note 1)
DS(on)
J
qJA
qJA
qJC
pk
= 25°C, V
, L = 1.0 mH, R
)
)
)
to Minimize Conduction Losses
Parameter
DD
(T
= 50 V, V
Steady
State
J
= 25°C unless otherwise noted)
G
T
T
t
= 25 W)
p
A
A
= 10 ms
= 25°C,
= 25°C
GS
T
T
T
T
T
T
T
T
T
A
A
A
A
A
A
C
C
C
= 10 V,
= 25°C
= 85°C
= 25°C
= 25°C
= 85°C
= 25°C
= 25°C
= 85°C
= 25°C
I
Symbol
DmaxPkg
T
V
dv/dt
V
J
E
I
P
P
P
, T
DSS
DM
T
I
I
I
I
GS
AS
D
D
D
S
D
D
D
L
stg
−55 to
Value
"20
180
175
260
9.2
7.2
2.1
7.8
6.0
1.5
8.0
25
45
35
50
45
45
20
1
Unit
V/ns
mJ
°C
°C
W
W
W
V
V
A
A
A
A
A
A
(Surface Mount)
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
1 2
CASE 369AA
V
Gate
(BR)DSS
STYLE 2
25 V
DPAK
1
3
Y
WW
T50N03R
G
ORDERING INFORMATION
Drain
Drain
4
MARKING DIAGRAMS
4
2
& PIN ASSIGNMENTS
http://onsemi.com
G
12.5 mW @ 10 V
19 mW @ 4.5 V
3
Source
(Straight Lead)
R
CASE 369D
DS(on)
N−Channel
= Year
= Work Week
= Device Code
= Pb−Free Package
STYLE 2
1
DPAK
2
Publication Order Number:
D
3
TYP
Gate
S
4
1
Drain
NTD50N03R/D
(Straight Lead)
Drain
CASE 369AC
4
2
I
3 IPAK
D
1
45 A
MAX
2 3
3
Source
4

Related parts for NTD50N03R-35G

NTD50N03R-35G Summary of contents

Page 1

... V N−Channel CASE 369D CASE 369AC DPAK 3 IPAK (Straight Lead) (Straight Lead) STYLE 2 MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain Gate Source Drain Source Drain Y = Year WW = Work Week T50N03R = Device Code G = Pb−Free Package ORDERING INFORMATION Publication Order Number: NTD50N03R/D ...

Page 2

... Gate−to−Source Charge Gate−to−Drain Charge 3. Surface−mounted on FR4 board using pad Cu. 4. Surface−mounted on FR4 board using the minimum recommended pad size. 5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. NTD50N03R (T = 25°C unless otherwise noted) J Symbol ...

Page 3

... Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge PACKAGE PARASITIC VALUES Source Inductance Drain Inductance Gate Inductance Gate Resistance 6. Switching characteristics are independent of operating junction temperatures. NTD50N03R (continued 25°C unless otherwise noted) J Symbol Test Condition t d(on ...

Page 4

... V , GATE−TO−SOURCE VOLTAGE (VOLTS) GS Figure 3. On−Resistance versus Gate−to−Source Voltage 2 1 1.6 1.4 1.2 1.0 0.8 0.6 −50 − JUNCTION TEMPERATURE (°C) J Figure 5. On−Resistance Variation with Temperature NTD50N03R 100 ≥ 0.030 T = 25° 25°C J 0.025 0.020 ...

Page 5

... R , GATE RESISTANCE (W) G Figure 9. Resistive Switching Time Variation versus Gate Resistance 1000 SINGLE PULSE 100 10 1 0.1 Figure 11. Maximum Rated Forward Biased NTD50N03R 25° iss oss 4 C rss Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge ...

Page 6

... ORDERING INFORMATION Order Number NTD50N03R NTD50N03RG NTD50N03RT4 NTD50N03RT4G NTD50N03R−1 NTD50N03R−1G NTD50N03R−35 NTD50N03R−35G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NTD50N03R P (pk ...

Page 7

... ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/ −T− SEATING K PLANE 0.13 (0.005 NTD50N03R PACKAGE DIMENSIONS DPAK CASE 369C−01 ISSUE O SEATING −T− PLANE SOLDERING FOOTPRINT* 6.20 3.0 0.244 0.118 2.58 0.101 1.6 6.172 0.243 ...

Page 8

... J 0.018 0.023 0.46 0.58 K 0.134 0.142 3.40 3.60 R 0.180 0.215 4.57 5.46 V 0.035 0.050 0.89 1.27 W 0.000 0.010 0.000 0.25 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NTD50N03R/D ...

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