PSMN010-55D,118 NXP Semiconductors, PSMN010-55D,118 Datasheet

MOSFET N-CH 55V 75A SOT-428

PSMN010-55D,118

Manufacturer Part Number
PSMN010-55D,118
Description
MOSFET N-CH 55V 75A SOT-428
Manufacturer
NXP Semiconductors
Series
TrenchMOS™r
Datasheet
1.PSMN010-55D118.pdf (9 pages)

Specifications of PSMN010-55D,118

Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
10.5 mOhm @ 25A, 10V
Drain To Source Voltage (vdss)
55V
Current - Continuous Drain (id) @ 25° C
75A
Vgs(th) (max) @ Id
2V @ 1mA
Gate Charge (qg) @ Vgs
55nC @ 5V
Input Capacitance (ciss) @ Vds
3300pF @ 20V
Power - Max
125W
Mounting Type
Surface Mount
Package / Case
DPak, TO-252 (2 leads+tab), SC-63
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
934055819118
PSMN010-55D /T3
PSMN010-55D /T3
Philips Semiconductors
FEATURES
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Logic level compatible
GENERAL DESCRIPTION
SiliconMAX products use the latest
Philips
achieve
on-state
package at each voltage rating.
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
The PSMN010-55D is supplied in
the
mounting package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
1 It is not possible to make connection to pin 2 of the SOT428 package.
2 Continuous current rating limited by package.
October 1999
N-channel logic level TrenchMOS
SYMBOL PARAMETER
V
V
V
V
I
I
P
T
D
DM
j
DSS
DGR
GS
GSM
D
, T
stg
SOT428
Trench
the
resistance
Drain-source voltage
Drain-gate voltage
Continuous gate-source
voltage
Peak pulsed gate-source
voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
lowest
(Dpak)
technology
in
possible
surface
each
to
PINNING
SYMBOL
PIN
tab
1
2
3
CONDITIONS
T
T
T
T
T
T
T
j
j
j
mb
mb
mb
mb
= 25 ˚C to 175˚C
= 25 ˚C to 175˚C; R
= 25 ˚C; V
= 100 ˚C; V
= 25 ˚C
= 25 ˚C
150 ˚C
gate
drain
source
drain
g
1
DESCRIPTION
transistor
1
GS
GS
d
s
= 5 V
= 5 V
GS
= 20 k
QUICK REFERENCE DATA
SOT428 (DPAK)
R
R
DS(ON)
DS(ON)
MIN.
- 55
-
-
-
-
-
-
-
-
10.5 m (V
V
12 m (V
I
DSS
Product specification
D
PSMN010-55D
1
= 75 A
= 55 V
tab
2
MAX.
240
125
175
75
55
55
57
3
15
20
2
GS
GS
= 5 V)
= 10 V)
Rev 1.200
UNIT
W
˚C
V
V
V
V
A
A
A

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PSMN010-55D,118 Summary of contents

Page 1

... Applications:- • d.c. to d.c. converters • switched mode power supplies The PSMN010-55D is supplied in the SOT428 (Dpak) surface mounting package. LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER ...

Page 2

... 175˚ 1 Resistive load Measured tab to centre of die Measured from source lead to source bond pad MHz Product specification PSMN010-55D MIN. MAX. UNIT - 264 MIN. TYP. MAX. UNIT - - 1 MIN. TYP. MAX. UNIT -55˚ 1 175˚C 0 -55˚ 2.3 - 7.4 10 0.02 ...

Page 3

... SYMBOL PARAMETER I Continuous source current S (body diode) I Pulsed source current (body SM diode) V Diode forward voltage SD t Reverse recovery time rr Q Reverse recovery charge rr October 1999 transistor CONDITIONS -dI /dt = 100 Product specification PSMN010-55D MIN. TYP. MAX. UNIT - - 240 A - 0. Rev 1.200 ...

Page 4

... Fig.6. Typical on-state resistance Product specification PSMN010-55D Transient thermal impedance, Zth j-mb (K/ 0.5 0.2 0.1 0.05 0. single pulse T 1E-05 1E-04 1E-03 1E-02 1E-01 Pulse width, tp (s) Fig.4. Transient thermal impedance. ...

Page 5

... I 10000 1000 100 100 120 140 160 180 Fig.12. Typical capacitances f f Product specification PSMN010-55D Threshold Voltage, VGS(TO) (V) maximum typical minimum 100 120 140 160 180 Junction Temperature, Tj (C) Fig.10. Gate threshold voltage. = f(T ); conditions mA Drain current, ID (A) minimum ...

Page 6

... V; parameter T F SDS GS October 1999 transistor Maximum Avalanche Current, I 100 10 VDD = 100 0.001 Fig.15. Maximum permissible non-repetitive avalanche current ( 0.8 0.9 1 1.1 1 Product specification PSMN010-55D ( prior to avalanche = 150 C 0.01 0.1 1 Avalanche time, t (ms versus avalanche time (t AS unclamped inductive load Rev 1.200 ...

Page 7

... REFERENCES IEC JEDEC EIAJ 7 Product specification PSMN010-55D SOT428 max. max. min. 2.95 0.7 10.4 0.2 0.2 0.5 9.6 2.55 0.5 EUROPEAN ISSUE DATE ...

Page 8

... Philips Semiconductors N-channel logic level TrenchMOS MOUNTING INSTRUCTIONS Dimensions in mm October 1999 transistor 7.0 7.0 2.15 2.5 4.57 Fig.17. SOT428 : soldering pattern for surface mounting . 8 Product specification PSMN010-55D 1.5 Rev 1.200 ...

Page 9

... Philips customers using or selling these products for use in such applications their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. October 1999 transistor 9 Product specification PSMN010-55D Rev 1.200 ...

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