STE100P STMicroelectronics, STE100P Datasheet

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... FAST ETHERNET 3.3V TRANSCEIVER 1 DESCRIPTION The STE100P, also referred to as STEPHY1 high performance Fast Ethernet physical layer in- terface for 10Base-T and 100Base-TX applica- tions. It was designed with advanced CMOS technology to provide a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Control- lers (MAC) and a physical media interface for 100Base-TX of IEEE802 ...

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... Link LED: On when a good link is detected, blinks when there activity ■ Full Duplex / Collision LED: On during Full Duplex operation. Blinks at 20Hz to indicate a collision ■ 2.4 Miscellaneous Standard 64-pin QFP package pinout ■ Figure 3. System Diagram of the STE100P Application 2/31 LEDs Serial EEPROM MAC STE100P STEPHY1 ...

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... Transmit Data. The Media Access Controller (MAC) drives data to the STE100P using these inputs. txd4 is monitored only in Symbol (5B) Mode. These signals must be synchronized to the tx_clk. Transmit Enable. The MAC asserts this signal when it drives valid data on the txd inputs. This signal must be synchronized to the tx_clk. ...

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... Transmit Coding Error. The MAC asserts this input when an error has occurred in the transmit data stream. When the STE100P is operating at 100 Mbps, the STE100P responds by sending invalid code symbols on the line. In Symbol (5B) Mode this pin functions as txd4. Receive Data. The STE100P drives received data on these outputs, synchro- nous to rx_clk ...

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... When cfg1 is High, Loopback mode is enabled and PR0: Reset (Active-Low). This input must be held low for a minimum reset the STE100P. During Power-up, the STE100P will be reset regardless of the state of this pin, and this reset will not be complete until after >1ms. Reset In Progress. This output is used to indicate when the device has completed power-up/reset and the registers and functions can be accessed ...

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... The functions of the five mf inputs are as shown in the table below. The logic level of mf0-4 will determine the value that the affected bits will have upon reset of the STE100P. The operating functions of cfg0, cfg1, and fde change depending on the state of mf0 (Auto-Negotiation enabled or disabled). Table 2 shows the relationship between cfg0, cfg1 and fde ...

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... PAD input is resistively pulled high then the corresponding LED output will be configured as an active low driver. These outputs are standard CMOS drivers and not open-drain. The STE100P PAD[4:0] inputs provide unique PHY address options. An address selection of all zeros (00000) will result in a PHY isolation condition as a result of power-on/reset, as documented for PR0 bit 10 ...

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... REGISTERS AND DESCRIPTORS DESCRIPTION There are 11 registers with 16 bits each supported for the STE100P. These include 7 basic registers which are defined according to the clause 22 “Reconciliation Sublayer and Media Independent Interface” and clause 28 “Physical Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair” of IEEE802 ...

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... ISOEN 0 – Normal operation. 1 – Isolate PHY from MII. Setting this control bit isolates the STE100P from the MII, with the exception of the serial management inter-face. When this bit is asserted, the STE100Pdoes not respond to TXD[3:0], TX-EN, and TX-ER inputs, and it presents a high impedance on its TX-CLK, RX-CLK, RX-DV, RX-ER, D[3:0], COL, and CRS outputs ...

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... Six bits manufacture’s model number. 3~0 REV Revision number of STE100P. Four bits manufacture’s revision number. PR4- ANA, Auto-Negotiation Advertisement 15 NXTPG Next Page ability. Always 0: since STE100P does not provide next page ability. 14 --- Reserved 10/31 Descriptions bits of the Organizationally Unique ...

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... Reserved 10 FC Flow Control function Ability. 1:supports PAUSE operation of flow control for full duplex link 100BASE-T4 Ability. Always 0: since STE100P doesn’t have 100BASE-T4 ability. 8 TXF 100Base-TX Full duplex Ability. 1: with 100Base-TX full duplex ability. 7 TXH 100Base-TX Half duplex Ability. 1: with 100Base-TX ability. ...

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... Link Partner’s Next Page ability. 0: link partner without next page ability. 1: link partner with next page ability STE100P’s next Page ability. Always 0, since STE100P without next page ability Page Received new page has been received new page has been received. ...

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... Disable the RX_ERR counter. 0: the receive error counter - RX_ERR is enabled. 1: the receive error counter - RX_ERR is disabled. 12 ANC Auto-Negotiation completed. This bit is the same as PR1:5. 0: the Auto-Negotiation process has not completed yet. 1: the Auto-Negotiation process has completed. Descriptions STE100P Default Val RW Type 0 RO/LH* 0 RO/LH* 0 RO/LH* ...

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... STE100P Table 5. Register Descriptions (continued) Bit # Name 11, 10 --- reserved 9 ENRLB Enable remote loop-back function. 1: enable 8 ENDCR Enable DC restoration. 0: disable DC restoration. 1: enable DC restoration. 7 ENRZI Enable the conversions between NRZ and NRZI. 0: disable the data conversion between NRZ and NRZI. 1: enable the data conversion of NRZI to NRZ in receiving and NRZ to NRZI in transmitting ...

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... DEVICE OPERATION The STE100P integrates the IEEE802.3u compliant functions of PCS (Physical Coding Sub-layer), PMA (Physical Medium Attachment), and PMD(Physical Medium Dependent) for 100Base-TX, and the IEEE802.3 compliant functions of Manchester encoding/decoding and transceiver for 10Base-T. All the functions and operation schemes are described in the following sections. ...

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... De-scrambling and Decoding of 5B/4B: The parallel 5B type data is passed to de-scrambler and 5B/4B decoder to return their original MII nibble type data. Carrier sensing: Carrier Sense(CRS) signal is asserted when the STE100P detects any 2 non-contiguous zeros within any 10 bit boundary of the receiving bit stream. CRS is de-asserted when ESD code-group or Idle code-group is detected ...

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... Since the power supply of the 100Base-TX and 10Base-T circuits are separated, the STE100P can turn off the circuit of either the 100Base-TX or 10Base-T when the other one of them is operating. There is also a Power Down mode which can be selected by PDEN in register PR0 bit 11 ...

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... The active low Reset input signal is required at least ensure proper reset operation. Second, for software reset, when bit 15 of register PR0 is set to 1, the STE100P will reset entire circuits and registers to their default values, then clear the bit 15 of PR0 to 0, and set the RIP output pin 29 to logic 1 ...

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... Note: The above LED connections are recommended for setting a Logic Level 1 or Logic Level 0 on the STE100P LED/PHY Address pins, for determining PHY address. 7.11 Preamble Suppression Preamble suppression mode in the STEPHY1 is indicated by a one in bit six of the PR1 Register determined that all PHY devices in the system support preamble suppression, then a preamble is not nec- essary for each management transaction ...

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... STE100P 8 ELECTRICAL SPECIFICATIONS AND TIMINGS Table 6. Absolute Maximum Ratings Parameter Supply Voltage(Vcc) Input Voltage Output Voltage Storage Temperature Ambient Temperature ESD Protection Table 7. General DC Specifications Symbol Parameter General DC Vcc Supply Voltage 10Base-T Voltage/Current Characteristics Vida10 Input Differential Accept Peak Voltage Vidr10 ...

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... Tflpw FLP Width Tflcpp Clock pulse to clock pulse period Tflcpd Clock pulse to Data pulse period - Number of pulses in one burst Tflbw Burst Width Tflbp FLP Burst period Test Condition 10Mbps 10Mbps Test Condition STE100P Min. Typ. Max. Units ±50 PPM 18 pF 100 ...

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... STE100P Figure 9. Fast Link Pulse timing Tflbw Table 8. AC Specifications Symbol Parameter 100Base-TX Transmitter AC Timings Specification Tjit TDP-TDN Differential Output Peak Jitter MII Management Clock Timing Specifications t1 MDC High Pulse Width t2 MDC Low Pulse Width t3 MDC Period t4 MDIO(I) Setup to MDC Rising ...

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... After RX-CLK t3 RX-CLK High Pulse Width (100 Mbits/s) RX-CLK High Pulse Width (10 Mbits/s) t4 RX-CLK Low Pulse Width (100 Mbits/s) RX-CLK Low Pulse Width (10 Mbits/s) t5 RX-CLK Period (100 Mbits/s) RX-CLK Period (10 Mbits/ Test Condition STE100P t3 Min. Typ. Max. Units 10 — — 200 ...

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... STE100P Figure 11. MII Receive Timing Table 8. AC Specifications Symbol Parameter MII Transmit Timing Specification t1 TX-ER,TX-EN,TXD[3:0] Setup to TX-CLK Rise t2 TX-ER,TX-EN,TXD[3:0] Hold After TX-CLK Rise Figure 12. MII Transmit Timing 24/31 Test Condition Min Typ. Max. Units — ...

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... End Receive Frame to Sampled Edge of RX-DV (10 Mbits/s) Rt4 End of Receive Frame to CRS Low (100 Mbits/s) End of Receive Frame to CRS Low (10 Mbits/s) Figure 13. Receive Timing Test Condition Min. — — — — — — — — STE100P Typ. Max. Units 300 250 ns 3.5 us 200 300 ns ...

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... STE100P Table 8. AC Specifications Symbol Parameter Transmit Timing Specification t1 TX-EN Sampled to CRS High (100 Mbits/s) TX-EN Sampled to CRS High (10 Mbits/s) t2 TX-EN Sampled to CRS Low (100 Mbits/s) TX-EN Sampled to CRS Low (10 Mbits/s) t3 Transmit Latency (100 Mbits/s) Transmit Latency (10 Mbits/s) t4 Sampled TX-EN Inactive to End ...

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... TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TXP out (Tx latency the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. Sym Min Typ t2A 10 - t2B 5 - t2C - 30 t2D - 40 t2E 60 100 STE100P Max Units - 160 ns 140 ns 27/31 ...

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... STE100P Figure 16. 10Base-T Half Duplex Transmit Timing TXP Table 10. Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TXP out (Tx latency) 28/31 Sym Min Typ t8A ...

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... TQFP64 OUTLINE AND MECHANICAL DATA TQFP64 ( 1.4mm 0.08mm ccc Seating Plane C K 0051434 E STE100P 29/31 ...

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... August 2004 September 2004 February 2005 30/31 15 Rev. A12 June 2003 has been migrated from ST-PRESS to EDOCS. 16 Changed the Style-sheet on the Rev. A13. 17 Wrong package corrected. 18 Due to Rev. 17 content was partially wrong. Now fixed. 19 Added part number “E-STE100P” (ECOPACK). Description of Changes ...

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