LAN8700I-AEZG SMSC, LAN8700I-AEZG Datasheet - Page 16

• Manufacturer Part Number: LAN8700I-AEZG
• Description: Ethernet ICs HIPERFRM ETHRNT PHY
• Manufacturer: SMSC
• Type: MII/RMII Ethernet Transceiverr

Specifications of LAN8700I-AEZG

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 802.3ab
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Supply Current (max): 39 mA, 81.6 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: QFN-36
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 2.2 (12-04-09)
SIGNAL NAME
SIGNAL NAME
CRS_DV
nINTSEL
Note 3.1
TX_ER/
CLKIN/
RXD3/
XTAL1
XTAL2
TXD4
nRST
RMII/
nINT/
COL/
Table 3.4 Boot Strap Configuration Inputs
On nRST transition high, the PHY latches the state of the configuration pins in this table.
TYPE
TYPE
IOPD
IOPU
IOPU
±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
I/O
O
I
Table 3.5 General Signals
DATASHEET
Digital Communication Mode: set the digital communications
mode of the PHY to RMII or MII. This signal is muxed with the
Collision signal (MII mode) and Carrier Sense/ receive Data Valid
(RMII mode)
nINT pin mode select: set the mode of pin 1.
Notes:For nINT mode, tie nINT/TXD4/TXER to VDDIO with a
resistor (see
on page
Notes:For TXD4/TXER mode, do not tie nINT/TXD4/TXER to
VDDIO or Ground.
LAN Interrupt – Active Low output. Place an external resistor
(see
page
Notes:
External Reset – input of the system reset. This signal is active
LOW. When this pin is deasserted, the mode register bits are
loaded from the mode pins as described in
Clock Input – 25 Mhz or 50 MHz external clock or crystal input.
In MII mode, this signal is the 25 MHz reference input clock
In RMII mode, this signal is the 50 MHz reference input clock
which is typically also driven to the RMII compliant Ethernet MAC
clock input.
Note:
Clock Output – 25 MHz crystal output.
Note:
Float for MII mode.
Pull up with a resistor to VDDIO for RMII mode (see
“Boot Strapping Configuration Resistors,” on page
Default, left floating pin 1 is nINT, active low interrupt output.
Pulled to VSS by a resistor, (see
Configuration Resistors,” on page
Transmit Error or Transmit data 4 (5B mode).
This signal is mux’d with TXER/TXD4
See
for additional details on Strapping options.
Table 4.3, “Boot Strapping Configuration Resistors,” on
32) pull-up to VCC 3.3V.
Section 4.10, "nINT/TX_ER/TXD4 Strapping," on page 31
16
32).
See
page 31
Float this pin if using an external clock being driven
through CLKIN/XTAL1
Table 4.3, “Boot Strapping Configuration Resistors,”
Section 4.10, "nINT/TX_ER/TXD4 Strapping," on
for additional details on Strapping options.
(Note
DESCRIPTION
DESCRIPTION
3.1) (continued)
Table 4.3, “Boot Strapping
32) pin 1 is TX_ER/TXD4,
SMSC LAN8700/LAN8700i
Section
®
Technology in a Small Footprint
5.4.9.2.
32) .
Table 4.3,
Datasheet