COM20020I3V-HT SMSC, COM20020I3V-HT Datasheet
COM20020I3V-HT
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COM20020I3V-HT Summary of contents
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... Software Programmable Node ID COM20020I 3V-DZD for 28 pin PLCC * Lead-Free RoHS Compliant package COM20020I 3V-HT for 48 pin TQFP Lead-Free RoHS Compliant package * TQFP package is recommended for new design SMSC COM20020I 3.3V Rev.E COM20020I 3.3V Rev.E 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM ...
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... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). ...
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... OPERATIONAL DESCRIPTION .....................................................................................................45 7 AXIMUM UARANTEED ATINGS 7 LECTRICAL HARACTERISTICS CHAPTER 8 TIMING DIAGRAMS .......................................................................................................................48 CHAPTER 9 PACKAGE OUTLINES ...................................................................................................................63 CHAPTER 10 APPENDIX A...................................................................................................................................65 CHAPTER 11 APPENDIX B...................................................................................................................................68 CHAPTER 12 APPENDIX C...................................................................................................................................69 12 OFTWARE DENTIFICATION OF THE SMSC COM20020I 3.3V Rev.E TABLE OF CONTENTS ........................................................................................................................12 ......................................................................................................................12 .....................................................................................................................15 ..................................................................................................................19 * .................................................................................................................45 ................................................................................................................45 COM20020I ............................................................69 EV AND EV Page 3 DATASHEET Revision 09-11-06 ...
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... Table 5 - DIAGNOSTIC STATUS REGISTER ..............................................................................................................29 Table 6 - COMMAND REGISTER ................................................................................................................................30 Table 7 - Address Pointer High Register .......................................................................................................................30 Table 8 - Address Pointer Low Register........................................................................................................................31 Table 9 - SUB ADDRESS REGISTER .......................................................................................................................31 Table 10 - Configuration Register ................................................................................................................................31 Table 11 - SETUP 1 REGISTER ..................................................................................................................................33 Table 12 - SETUP 2 REGISTER ..................................................................................................................................34 SMSC COM20020I 3.3V Rev.E LIST OF FIGURES LIST OF TABLES Page 4 DATASHEET Revision 09-11-06 ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM Chapter 1 General Description SMSC's COM20020I member of the family of Embedded ARCNET Controllers from Standard Microsystems Corporation. The device is a general purpose communications controller for networking microcontrollers and intelligent peripherals in industrial and embedded control environments using an ARCNET protocol engine. The flexible microcontroller and media interfaces, eight-page message support, and extended temperature range of the COM20020I 3V make it the only true network controller optimized for use in industrial and embedded applications ...
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... PACKAGE TYPE Plastic, LJP = PLCC PACKAGE TYPE Plastic, LJP = PLCC COM20020I 3V P TEMP RANGE: TEMP RANGE Industrial: -40° 75° C DEVICE TYPE: 20020 = Universal Local Area Network DEVICE TYPE: 20019 = Universal Local Area Network Controller RAM) SMSC COM20020I 3.3V Rev nWR/DIR 26 27 ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM AD0 1 AD1 2 N/C 3 AD2 4 N/C 5 VSS VDD VSS SMSC COM20020I 3.3V Rev.E COM20020I COM20020I 3V 48 PIN TQFP 48 PIN TQFP NOTE: BUSTMG pin is only TQFP package Page 7 DATASHEET 36 nCS 35 VDD 34 nINTR 33 N/C 32 VDD 31 nRESET 30 VSS 29 nTXEN 28 ...
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... Select - 26 Read/Write Bus Timing Select SMSC COM20020I 3.3V Rev.E SYMBOL I/O MICROCONTROLLER INTERFACE On a non-multiplexed mode, A0-A2 are address A0/nMUX IN input bits. (A0 is the LSB multiplexed A1 IN address/data bus, nMUX tied Low left open, and ALE is tied to the Address Latch Enable signal. ...
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... N/C 14-17, 19, 27, 33, 35, 38, 40, 42, 47, 48 SMSC COM20020I 3.3V Rev.E SYMBOL I/O TRANSMISSION MEDIA INTERFACE In Normal Mode, these active low signals carry the nPULSE1 OUT transmit data information, encoded in pulse format as DIPULSE waveform. In Backplane Mode, the nPULSE1 signal driver is programmable (push/pull ...
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... DID refers to the destination identification. - SOH refers to the start of header character; preceeds all data packets. * Reconfig timer is programmable via setup2 register bits 1, 0. Note - All time values are valid for 5 Mbps. SMSC COM20020I 3.3V Rev.E Power On Send Reconfigure Burst Read Node ID ...
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... ARCNET core operation. This clock generator is called “clock multiplier”. Changing the CKUP bit must be one time or less after releasing hardware reset. SMSC COM20020I 3.3V Rev.E CLOCK DATA RATE Div Mbps Div ...
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... For a typical system using RG62 coax in a baseband system, a one way cable propagation delay of 15.5 μS translates to a distance of about 2 miles. The flow chart in Figure 1 uses a value of 37.4uS (15.5 + 15.5 + 6.4) to determine if any node will respond. SMSC COM20020I 3.3V Rev.E Page 12 DATASHEET ...
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... An SID (Source ID) character Two (repeated) DID (Destination ID) characters A single COUNT character which is the 2's complement of the number of data bytes to follow if a short packet is sent, or 00H followed by a COUNT character if a long packet is sent. SMSC COM20020I 3.3V Rev.E DID DID Page 13 DATASHEET ...
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... ALERT BURST ACK Negative Acknowledgements A Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the following sequence: An ALERT BURST A NAK (Negative Acknowledgement--ASCII code 15H) character ALERT BURST NAK SMSC COM20020I 3.3V Rev.E DID COUNT data data Page 14 DATASHEET 16 15 ...
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... Data Register does not load new data from the internal RAM. During a write operation, the data is stored in the data register and then written into memory. Whenever the pointer is loaded for reads with a new value, data is immediately prefetched to prepare for the first read operation. SMSC COM20020I 3.3V Rev.E Page 15 DATASHEET ...
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... A15 RESET nRD nWR nINT1 8051 RXIN TXEN nPULSE1 nPULSE2 GND BACKPLANE CONFIGURATION FIGURE A Figure 2 - Multiplexed, 8051-Like Bus Interface With RS-485 Interface SMSC COM20020I 3.3V Rev.E COM20022 AD0-AD2, D3-D7 A2/BALE RXIN nCS 75176B or nRESET nTXEN Equiv. nPULSE1 nRD/nDS nPULSE2 nWR/DIR GND ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM XTAL1 XTAL2 D0- nRES nIOS R/nW nIRQ1 6801 RXIN nTXEN nPULSE1 nPULSE2 Figure 3 - Non-Multiplexed, 6801-Like Bus Interface With RS-485 Interface SMSC COM20020I 3.3V Rev.E COM20022 D0-D7 A0/nMUX A1 A2/BALE nCS nPULSE1 nRESET nPULSE2 nRD/nDS nWR/nDIR nINTR 27 pF +5V HYC9068 or 10 HYC9088 ...
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... CPU Read and Write function defined as: BUSTMG = 0, the High Speed CPU Read and Write operations are enabled; BUSTMG = 1, the High Speed CPU Read and Write operations are disabled if the RBUSTMG bit BUSTMG = 1 and RBUSTMG = 1, High Speed CPU Read operations are enabled (see definition of RBUSTMG bit below). SMSC COM20020I 3.3V Rev.E VALID VALID Page 18 ...
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... Common Mode Rejection. The Traditional Hybrid Interface uses circuits like SMSC's HYC9068 or HYC9088 to transfer the pulse-encoded data between the cable and the COM20020I 3V. The COM20020I 3V transmits a logic "1" by generating two 100nS non-overlapping negative pulses, nPULSE1 and nPULSE2. ...
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... Equiv. COM20022I 3V Figure 5 - COM20020I 3V Network Using RS-485 Differential Transceivers 20MHZ CLOCK (FOR REF. ONLY) 100ns nPULSE1 nPULSE2 200ns DIPULSE RXIN Figure 6 - Dipulse Waveform For Data Of 1-1-0 SMSC COM20020I 3.3V Rev.E +VCC +VCC RBIAS RBIAS COM20022I 100ns 400ns Page 20 DATASHEET RT +VCC RBIAS ...
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... The polarity determination is made at power on reset and is valid only for Backplane Mode operation. The nPULSE2 pin should remain grounded at all times if an active high polarity is desired. SMSC COM20020I 3.3V Rev coupled configuration Page 21 DATASHEET ...
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... ADDRESS DECODING CIRCUITRY AD0-AD2, D3-D7 STATUS/ nINTR COMMAND REGISTER RESET nRESET LOGIC nRD/nDS nWR/DIR BUS ARBITRATION nCS CIRCUITRY SMSC COM20020I 3.3V Rev RAM MICRO- SEQUENCER AND WORKING REGISTERS OSCILLATOR RECONFIGURATION NODE ID LOGIC TIMER Figure 7 - Internal Block Diagram Page 22 DATASHEET ADDITIONAL REGISTERS ...
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... Note: For more detailed information on Cabling options including RS-485, transformer-coupled RS-485 and Fiber Optic interfaces, please refer to TN7-5 – Cabling Guidelines for the COM20020I 3V ULANC, available from Standard Microsystems Corporation. SMSC COM20020I 3.3V Rev.E Table 1 - Typical Media NOMINAL ATTENUATION PER 1000 FT. ...
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... NODE ID NID7 NID6 SETUP1 P1 MODE FOUR NAKS NEXT ID NXT ID7 NXT SETUP2 RBUS-TMG Note*: (R/W) These bits can be Written or Read. For more information see Appendix C. SMSC COM20020I 3.3V Rev.E Table 2 - Read Register Summary READ X/TA POR TEST TOKEN RCV- EXC-N ACT ...
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... The Tentative ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly (please refer to the Configuration Register and SUB ADR Register). The Tentative ID Register can be used while the node is on-line to build a network map of those nodes existing on the network. It minimizes the need for operator SMSC COM20020I 3.3V Rev.E Table 3 - Write Register Summary WRITE ...
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... The COM20020I 3V Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6, are software compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the Extended Timeout status was provided in bits 5 and 6 of the Status Register. In the COM20020I 3V, the COM20020, the COM90C66, and the COM90C165, COM20020-5, COM20051 and COM20051+ these bits exist in and are controlled by the Configuration Register ...
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... For other data rates, scale the time-out period time values accordingly; the maximum node count remains the same. RCNTM1 Note*: The node ID value 255 must exist in the network for the 26.25 mS time-out to be valid. SMSC COM20020I 3.3V Rev.E the SUBAD1and SUBAD0 in the Sub-Address register are also changed. TIME-OUT MAX NODE PERIOD RCNTM0 0 ...
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... Message Acknowledged 0 Transmitter TA Available SMSC COM20020I 3.3V Rev.E Table 4 - STATUS REGISTER DESCRIPTION This bit, if high, indicates that the receiver is not enabled because either an "Enable Receive to Page fnn" command was never issued packet has been deposited into the RAM buffer page fnn as specified by the last "Enable Receive to Page fnn" ...
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... New Next ID NEW NXTID 0 (Reserved) SMSC COM20020I 3.3V Rev.E DESCRIPTION This bit, if high, indicates that a past reconfiguration was caused by this node set when the Lost Token Timer times out, and should be typically read following an interrupt caused by RECON. Refer to the Improved Diagnostics section for further detail. ...
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... Clear Receive Interrupt 0001 1000 Start Internal Operation SMSC COM20020I 3.3V Rev.E Table 6 - COMMAND REGISTER DESCRIPTION This command is used only in the Command Chaining operation. Please refer to the Command Chaining section for definition of this command. This command will cancel any pending transmit command (transmission that has not yet started) and will set the TA (Transmitter Available) status bit to logic " ...
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... CCHEN This bit, if high, enables the Command Chaining operation of the device. Please refer to the Command Chaining section for further details. A low level on this bit ensures software compatibility with previous SMSC ARCNET devices. Page 31 DATASHEET Please refer to the Sequential Register ...
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... Extended Timeout 1,2 2 Backplane 1,0 Sub Address 1,0 SMSC COM20020I 3.3V Rev.E SYMBOL DESCRIPTION TXEN When low, this bit disables transmissions by keeping nPULSE1, nPULSE2 if in non-Backplane Mode, and nTXEN pin inactive. When high, it enables the above signals to be activated during transmissions. This bit defaults low upon reset ...
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... Receive All 3,2,1 Clock Prescaler Bits 3,2,1 0 Slow Arbitration Select SMSC COM20020I 3.3V Rev.E Table 11 - SETUP 1 REGISTER SYMBOL DESCRIPTION P1MODE This bit determines the type of PULSE1 output driver used in Backplane Mode. When high, a push/pull output is used. When low, an open drain output is used. The default is open drain ...
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... Clock Multiplier 3 Enhanced Functions 2 No Synchronous SMSC COM20020I 3.3V Rev.E Table 12 - SETUP 2 REGISTER SYMBOL DESCRIPTION RBUSTMG This bit is used to Disable/Enable the High Speed CPU Read function for High Speed CPU bus support. RBUSTMG=0: Disable (Default), RBUSTMG=1: Enable. That is, if BUSTMG (pin 26: Only for TQFP package and RBUSTMG = 1, High Speed CPU Read operations are enabled ...
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... RAM. The integration of RAM represents significant cost savings because it isolates the system designer from the changing costs of external RAM and it minimizes reliability problems, assembly time and costs, and layout complexity. SMSC COM20020I 3.3V Rev.E SYMBOL DESCRIPTION RCNTM1,0 These bits are used to program the reconfiguration timer as a function of maximum node count ...
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... Even if the Command Chaining operation is being used, 512 bytes is still guaranteed to be free because Command Chaining only SMSC COM20020I 3.3V Rev.E Page 36 DATASHEET ...
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... N represents the number of information bytes in the message, or for long packets, the value 0, indicating that it is indeed a long packet. In the latter case, Address 3 (COUNT) would contain the value 512-N, where N represents the number of information bytes in the message. SMSC COM20020I 3.3V Rev.E Page 37 DATASHEET ...
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... Transmit from Page fnn" command, which resets the TA and TMA bits to logic "0". If the message is not a BROADCAST, the COM20020I 3V automatically sends a FREE BUFFER ENQUIRY to the destination node in order to send the message. At this point, one of four possibilities may SMSC COM20020I 3.3V Rev.E ADDRESS SID ...
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... RAM buffer other than the SID and DID. Once the packet is received and stored correctly in the selected buffer, the COM20020I 3V sets the RI bit to logic "1" to signal the microcontroller that the reception is complete. SMSC COM20020I 3.3V Rev.E Page 39 DATASHEET ...
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... Through the use of a dual two-level FIFO, commands to be transmitted and received, as well as the status bits, are pipelined. In order for the COM20020I compatible with previous SMSC ARCNET device drivers, the device defaults to the non-chaining mode. In order to take advantage of the Command Chaining operation, the Command Chaining Mode must be enabled via a logic " ...
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... The COM20020I 3V contains digital filter circuitry and a Schmitt Trigger on the nRESET signal to reject glitches in order to ensure fault-free operation. The COM20020I 3V supports two reset options; software and hardware reset. A software reset is generated when a SMSC COM20020I 3.3V Rev.E Page 41 DATASHEET ...
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... Once it is determined that the ID in the Node ID Register is unique, the software should write a logic "1" to bit 5 of the Configuration Register to enable the basic transmit function. This allows the node to join SMSC COM20020I 3.3V Rev.E Page 42 ...
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... If an external crystal is used, two capacitors are needed (one from each leg of the crystal to ground). No external resistor is required, since the COM20020I 3V contains an internal resistor. The crystal must have an accuracy of 0.020% SMSC COM20020I 3.3V Rev.E No receive activity is seen and the basic transmit function is enabled. ...
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... The XTAL2 side of the crystal may be loaded with a single 74HC-type buffer in order to generate a clock for other devices. The user may attach an external TTL clock, rather than a crystal, to the XTAL1 signal. In this case, a 390Ω pull-up resistor is required on XTAL1, while XTAL2 should be left unconnected. SMSC COM20020I 3.3V Rev.E Page 44 DATASHEET Revision 09-11-06 ...
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... D3-D7, nINTR, nPULSE1 in Push/Pull Mode, nPULSE2) High Output Voltage 2 (AD0-AD2, D3-D7, nINTR, nPULSE1 in Push/Pull Mode, nPULSE2) Low Output Voltage 3 (nPULSE1 in Open-Drain Mode) Dynamic V Supply DD Current SMSC COM20020I 3.3V Rev.E SYMBOL MIN TYP MAX V -0.3 0.8 IL1 V 2.0 5.5 IH1 V -0.3 0.2xV IL2 V ...
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... A1, AD0-AD2, D3-D7, XTAL1, BUSTMG) CAPACITANCE (T = 25° 1MHz Output and I/O pins capacitive load specified as follows: PARAMETER SYMBOL Input Capacitance Output Capacitance 1 (All outputs except XTAL2) SMSC COM20020I 3.3V Rev.E SYMBOL MIN TYP MAX I 80 200 P I ± 0V) DD MIN ...
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... Inputs are driven at 2.4V for logic "1" and 0.4 V for logic "0" except XTAL1 pin. Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0". SMSC COM20020I 3.3V Rev.E Outputs: t 2.0V 0.8V 2.0V 0.8V ...
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... COM20020 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 11 - Multiplexed Bus, 68xx-Like Control Signals; Read Cycle SMSC COM20020I 3.3V Rev.E VALID DATA VALID t1 t2, t4 ...
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... Data Register requires a minimum of 5T leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Figure 12 - Multiplexed Bus, 80xx-Like Control Signals; Read Cycle SMSC COM20020I 3.3V Rev.E VALID DATA VALID t1 t2 ...
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... Write cycle for Address Pointer Low Register occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 13 - Multiplexed Bus, 68xx-Like Control Signals; Write Cycle SMSC COM20020I 3.3V Rev.E VALID DATA VALID t2 t12 ...
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... Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5T leading edge of nWR. Figure 14 - Multiplexed Bus, 80xx-Like Control Signals; Write Cycle SMSC COM20020I 3.3V Rev.E VALID DATA t2, t4 t10 t5 ...
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... Data Register requires a minimum of 5T leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Figure 15 - Non-Multiplexed Bus, 80xx-Like Control Signals; Read Cycle SMSC COM20020I 3.3V Rev.E VALID t1 t3 Note 3 t5 ...
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... Data Register requires a minimum of 5T leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Figure 16 - Non-Multiplexed Bus, 80xx-Like Control Signals; Read Cycle SMSC COM20020I 3.3V Rev.E VALID t1 t3 Note 3 t5 ...
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... COM20020 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 17 - Non-Multiplexed Bus, 68xx-Like Control Signals; Read Cycle SMSC COM20020I 3.3V Rev.E VALID ...
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... COM20020 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 18 - Non-Multiplexed Bus, 68xx-Like Control Signals; Read Cycle SMSC COM20020I 3.3V Rev.E VALID t10 ...
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... Register requires a minimum of 5T leading edge of the next nWR. Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5T leading edge of nWR. Figure 19 - Non-Multiplexed Bus, 80xx-Like Control Signals; Write Cycle SMSC COM20020I 3.3V Rev.E VALID VALID DATA ...
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... Register requires a minimum of 5T leading edge of the next nWR. Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5T leading edge of nWR. Figure 20 - Non-Multiplexed Bus, 80xx-Like Control Signals; Write Cycle SMSC COM20020I 3.3V Rev.E VALID VALID DATA ...
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... Any cycle occurring after a write to the Address Pointer Low Register requires a minimum the next nDS. Write cycle for Address Pointer Low Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 21 - Non-Multiplexed Bus, 68xx-Like Control Signals; Write Cycle SMSC COM20020I 3.3V Rev.E VALID t10 t8 ...
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... Any cycle occurring after a write to the Address Pointer Low Register requires a minimum the next nDS. Write cycle for Address Pointer Low Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 22 - Non-Multiplexed Bus, 68xx-Like Control Signals; Write Cycle SMSC COM20020I 3.3V Rev.E VALID t10 t8 ...
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... Beginning of Last Bit Time to nTXEN High t6 RXIN Active Pulse Width t7 RXIN Period t8 RXIN Inactive Pulse Width Note: Use Only 2.5 Mbps Figure 23 – Normal Mode Transmit Or Receive Timing SMSC COM20020I 3.3V Rev (These signals are to and from the hybrid) Page 60 DATASHEET ...
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... *t3, t11 = ** +/- **t13 = x T +/- Figure 24 – Backplane Mode Transmit or Receive Timing (THESE SIGNALS ARE TO AND FROM THE DIFFERENTIAL DRIVER OR THE CABLE) SMSC COM20020I 3.3V Rev t10 t12 t11 Parameter Page 61 DATASHEET t13 t8 LAST BIT (400 nS BIT TIME) min typ max ...
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... Pulse Width*** t2 nINTR High to Next nINTR Low Note period of external XTAL oscillation frequency. XTL Note**: T is period of Data Rate (i.e. at 2.5 Mbps Note***: When the power is turned on measured from stable XTAL oscillation after V DD SMSC COM20020I 3.3V Rev 1.0V min -200 + - t2 min ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM Chapter 9 Package Outlines OTES dim ensions are in inches ircle indicating pin 1 can appear on a top surface as show n on the draw ing or right above beveled edge. Figure Pin PLCC Package Dimensions SMSC COM20020I 3.3V Rev.E PIN 28L ...
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... 0.50 Basic o θ 0.17 R1 0.08 R2 0.08 ccc ~ ccc ~ Note 1: Controlling Unit: millimeter SMSC COM20020I 3.3V Rev.E Figure Pin TQFP Package Outline MAX ~ 1.6 Overall Package Height 0.10 0.15 Standoff 1.40 1.45 Body Thickness 9.00 9.20 X Span 1 4.50 4. Span Measure from Centerline 2 7 ...
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... CKP3-1 may cause spike noise to appear on the output clock line. Setting the EF bit will include flip-flops inserted between the Configuration register and Pre-Scalar for synchronizing the CKP3-1 with Pre-Scalar’s internal clocks. SMSC COM20020I 3.3V Rev.E Page 65 DATASHEET Revision 09-11-06 ...
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... This is illustrated in Figure 29. EF=0 TA/RI bit Setting Pulse nINTR pin EF=1 TA/RI bit Setting Pulse nINTR pin Figure 29 - Effect Of The EF Bit On The TA/RI Bit SMSC COM20020I 3.3V Rev.E Tx/Rx completed prohibition period Tx/Rx completed Page 66 DATASHEET Revision 09-11-06 ...
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... This is resolved by changing the logic to reset the Mask register both by the hard reset and by the soft reset. The soft reset is activated by the Node-ID register going to 00h or by the RESET bit going to High in the Configuration register. This solution is Enabled/Disabled by the EF bit. SMSC COM20020I 3.3V Rev.E Page 67 DATASHEET ...
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... SA15-SA4 P 12 SD7-SD0 A 8 nIOR nIOW SA2-SA0 3 IRQm nIOCS16 DRQn nDACK TC nREFRESH RESETDRV Figure 30 - Example Of Interface Circuit Diagram To ISA Bus SMSC COM20020I 3.3V Rev.E LS688x2 12 bit Comparators Q I/O Address Seeting (DIP Switches) P=Q 12 LS245 A 16 bit Bus Transceivers DIR 3 Schmitt-Trigger Buffer ...
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... The value read from Register-5 must be 0x00. 3. Write 0xC0 to Register-5 4. Read Register- the value read from Register-5 is 0x80 then the part is a COM20020I 3V Rev the value read from Register-5 is 0xC0 then the part is a COM20020I 3V Rev E SMSC COM20020I 3.3V Rev.E Page 69 DATASHEET Revision 09-11-06 ...