LAN9313-NU SMSC, LAN9313-NU Datasheet - Page 147

• Manufacturer Part Number: LAN9313-NU
• Description: Ethernet ICs Three Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Three Port Managed Ethernet Switchr

Specifications of LAN9313-NU

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0 V
• Supply Current (max): 155 mA, 270 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
SMSC LAN9313/LAN9313i
13.1
000h - 04Ch
ADDRESS
068h - 070h
078h - 088h
094h - 098h
OFFSET
05Ch
08Ch
09Ch
0A0h
0A4h
0A8h
050h
054h
058h
060h
064h
074h
090h
The System CSR’s are directly addressable memory mapped registers with a base address offset
range of 050h to 2DCh. These registers are accessed through the I
MIIM/SMI serial interface. For more information on the various LAN9313/LAN9313i modes and their
corresponding address configurations, see
Table 13.1
reset to their default value on the assertion of a chip-level reset.
The System CSR’s can be divided into 8 sub-categories. Each of these sub-categories contains the
System CSR descriptions of the associated registers. The register descriptions are categorized as
follows:
System Control and Status Registers
Section 13.1.1, "Interrupts," on page 151
Section 13.1.2, "GPIO/LED," on page 155
Section 13.1.3, "EEPROM," on page 160
Section 13.1.4, "IEEE 1588," on page 164
Section 13.1.5, "Switch Fabric," on page 192
Section 13.1.6, "PHY Management Interface (PMI)," on page 207
Section 13.1.7, "Virtual PHY," on page 209
Section 13.1.8, "Miscellaneous," on page 224
lists the System CSR’s and their corresponding addresses in order. All system CSR’s are
PMI_ACCESS
Table 13.1 System Control and Status Registers
BYTE_TEST
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
FREE_RUN
SYMBOL
PMI_DATA
GPT_CFG
GPT_CNT
IRQ_CFG
HW_CFG
INT_STS
ID_REV
INT_EN
DATASHEET
147
Section 2.3, "Modes of Operation," on page
Reserved for Future Use
Chip ID and Revision Register,
Interrupt Configuration Register,
Interrupt Status Register,
Interrupt Enable Register,
Reserved for Future Use
Byte Order Test Register,
Reserved for Future Use
Hardware Configuration Register,
Reserved for Future Use
General Purpose Timer Configuration Register,
Section 13.1.8.4
General Purpose Timer Count Register,
Reserved for Future Use
Free Running Counter Register,
Reserved for Future Use
PHY Management Interface Data Register,
Section 13.1.6.1
PHY Management Interface Access Register,
Section 13.1.6.2
REGISTER NAME
2
Section 13.1.1.2
C/SPI serial interfaces or the
Section 13.1.8.2
Section 13.1.1.3
Section 13.1.8.1
Section 13.1.1.1
Section 13.1.8.6
Section 13.1.8.3
Revision 1.7 (06-29-10)
Section 13.1.8.5
23.