LAN9215-MZP SMSC, LAN9215-MZP Datasheet - Page 104

• Manufacturer Part Number: LAN9215-MZP
• Description: Ethernet ICs 16-BIT NON-PCI 10/100 ETHERNET CTRL
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9215-MZP

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 69 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 2.7 (03-15-10)
5.4.2
31-16
BITS
BITS
15-0
1-0
5
4
3
2
Deferral Check (DFCHK). When set, enables the deferral check in the MAC. The MAC will abort the
transmission attempt if it has deferred for more than 24,288 bit times. Deferral starts when the
transmitter is ready to transmit, but is prevented from doing so because the CRS is active. Defer time
is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and
then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts. When
reset, the deferral check is disabled in the MAC and the MAC defers indefinitely.
Reserved
Transmitter enable (TXEN). When set, the MAC’s transmitter is enabled and it will transmit frames
from the buffer onto the cable.
When reset, the MAC’s transmitter is disabled and will not transmit any frames.
Receiver Enable (RXEN). When set (1), the MAC’s receiver is enabled and will receive frames from
the internal PHY.
When reset, the MAC’s receiver is disabled and will not receive any frames from the internal PHY.
Reserved
Reserved
Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of
the LAN9215 device. The content of this field is undefined until loaded from the EEPROM at power-
on. The host can update the contents of this field after the initialization process has completed.
ADDRH—MAC Address High Register
The MAC Address High register contains the upper 16-bits of the physical address of the MAC. The
contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM
Controller if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0])
is loaded from address 0x05 of the EEPROM. The second byte (bits [15:8]) is loaded from address
0x06 of the EEPROM. Please refer to
details the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the
Ethernet physical address.
Offset:
Default Value:
2
0000FFFFh
DATASHEET
Section 4.6
104
DESCRIPTION
DESCRIPTION
Attribute:
Size:
for more information on the EEPROM. Section
16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support
R/W
32 bits
SMSC LAN9215
Datasheet
5.4.3