MAX4357ECD+ Maxim Integrated Products, MAX4357ECD+ Datasheet - Page 11

• Manufacturer Part Number: MAX4357ECD+
• Description: Analog & Digital Crosspoint ICs 32 x 16 Nonblocking Video Crosspoint Swi
• Manufacturer: Maxim Integrated Products

Specifications of MAX4357ECD+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SWITCHING CHARACTERISTICS
((V
ply, R
Note 1: Associated output voltage may be determined by multiplying the input voltage by the specified gain (A
Note 2: Logic-level characteristics apply to the following pins: DIN, DOUT, SCLK, CE, UPDATE, RESET, A3–A0, MODE, and AOUT.
Note 3: Switching transient settling time is guaranteed by the settling time (t
Note 4: Input test signal: 3.58MHz sine wave of amplitude 40IRE superimposed on a linear ramp (0 to 100IRE). IRE is a unit of
Note 5: All devices are 100% production tested at T
Delay: UPDATE to Video Out
Delay: UPDATE to AOUT
Delay: SCLK to DOUT Valid
Delay: Output Disable
Delay: Output Enable
Setup: CE to SCLK
Setup: DIN to SCLK
Hold Time: SCLK to DIN
Minimum High Time: SCLK
Minimum Low Time: SCLK
Minimum Low Time: UPDATE
Setup Time: UPDATE to SCLK
Hold Time: SCLK to UPDATE
Setup Time: MODE to SCLK
Hold Time: MODE to SCLK
Minimum Low Time: RESET
Delay: RESET
CC
L
- V
32 x 16 Nonblocking Video Crosspoint Switch
= 150Ω to AGND, C L = 100pF, A
offset voltage.
ing the switch matrix.
video-signal amplitude developed by the International Radio Engineers: 140IRE = 1.0V.
EE
PARAMETER
) = +4.5V to +10.5V, V
______________________________________________________________________________________
DD
= +2.7V to +5.5V, DGND = AGND = 0, V
SYMBOL
t
t
t
t
PdHOeVo
PdLOeVo
t
t
t
PdUdAo
t
t
t
PdUdVo
t
MnHCk
HdHUd
t
MnLRst
t
MnLCk
MnLUd
SuHUd
t
t
t
PdDo
t
HdMd
PdRst
SuMd
V
SuCe
HdDi
SuDi
= +1V/V, and T
V
MODE = 0, time to AOUT = low after
UPDATE = low
V
Output disabled, 1kΩ pulldown to AGND,
V
Rising edge of UPDATE to falling edge of
SCLK
Falling edge of SCLK to falling edge of
UPDATE
Minimum time from clock edge to MODE
with valid data clocking
Minimum time from clock edge to MODE
with valid data clocking
10kΩ pulldown to AGND
Logic state change in DOUT on active
SCLK edge
IN
OUT
IN
A
= +25°C. Specifications over temperature limits are guaranteed by design.
= 0.5V step
= 0.5V
= 0.5V, 1kΩ pulldown to AGND
A
= T
MIN
CONDITIONS
- T
MAX
, unless otherwise noted. Typical values are at T
S
) specification. Switching transient is a result of updat-
IN
_ = 0 for dual supplies, V
with I/O Buffers
MIN
100
100
100
100
100
100
100
100
100
IN
_ = +1.75V for single sup-
TYP
200
300
200
30
30
V )
and adding output
MAX
200
450
200
800
100
300
600
800
A
= +25°C.)
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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