LTC6907CS6 Linear Technology, LTC6907CS6 Datasheet - Page 8

• Manufacturer Part Number: LTC6907CS6
• Manufacturer: Linear Technology
• Type: Silicon Oscillatorr

Specifications of LTC6907CS6

• Mounting Style: Surface Mount
• Screening Level: Commercial
• Product Length (mm): 2.9mm
• Product Depth (mm): 1.75mm
• Product Height (mm): 0.9mm
• Package / Case: TSOT-23
• Lead Free Status / RoHS Status: Not Compliant

APPLICATIO S I FOR ATIO
LTC6907
8
Selecting R
The LTC6907 contains a master oscillator followed by a
digital divider (see Block Diagram). R
master oscillator frequency and the three level DIV pin sets
the divider ratio, N. The range of frequencies accessible in
each divider ratio overlap, as shown in Figure 7. This
figure is derived from the equations in Table 1. For any
given frequency, power can be minimized by minimiz-
ing the master oscillator frequency. This implies maxi-
mizing R
N . The relationship between R
power consumption is shown in Figure 8. The supply
current decreases for large values of R
section titled “Jitter and Divide Ratio.”
Minimizing Power Consumption
The supply current of the LTC6907 has four current
components:
An approximate expression for the total supply current is:
V
temperature. This behavior is shown in the Typical Perfor-
mance Characteristics.
Power can be minimized by maximizing R
the load on the OUT pin and operating at lower frequen-
cies. Figure 9 shows total supply current vs frequency
under typical conditions. Below 100kHz the load current is
negligible for the 5pF load shown.
I
I
o o r in terms of V
+
+
SET
,
≅ µ +
• Constant (Independent V
• Proportional to I
• Proportional to V
• Proportional to V
≅ µ +
7
7
is approximately 650mV at 25°C, but varies with
A
A
SET
6
6
SET
•
•
and using the lowest possible divider ratio,
I
R
SET
V
SET
SET
SET
and the Divider Ratio
+
,
+
V
U
SET
+
V
+
+
+
, ƒ
•
and R
ƒ
•
(which is the current in R
OUT
OUT
ƒ
U
OUT
LOAD
•
and C
+
, ƒ
(
• •
C
SET
(
LOAD
C
OUT
LOAD
, N and the unloaded
W
LOAD
and C
+
SET
+
5
SET
pF
5
SET
determines the
pF
)
LOAD
. Refer to the
+
)
, minimizing
+
2
U
•
2
)
R
V
•
LOAD
R
SET
+
V
LOAD
+
)
Guarding Against PC Board Leakage
The LTC6907 uses relatively large resistance values for
R
the SET pin current is typically only 13µA. Thus, only 13nA
leaking into the SET pin causes a 0.1% frequency error.
Similarly, 500M of leakage resistance across R
(1000 • R
Achieving the highest accuracy requires controlling po-
tential leakage paths. PC board leakage is aggravated by
both dirt and moisture. Effective cleaning is a good first
step to minimizing leakage.
Another effective method for controlling leakage is to shunt
the leakage current away from the sensitive node through
a low impedance path. The LTC6907 provides a signal on
the GRD pin for this purpose. Figure 10 shows a PC board
SET
to minimize power consumption. For R
10000
1000
Figure 7. R
Figure 8. Unloaded Supply Current vs R
SET
160
140
120
100
100
80
60
40
20
10
0
10
10
) causes the same 0.1% error.
SET
vs Desired Output Frequency
R
I
R
SUPPLY
SET
SET
100
100
(kΩ)
(kΩ)
C
V
DIV = –1
T
LOAD
+
A
= 3V
= 25°C
:
= 0
6907 F08
6907 F07
÷1
÷3
÷10
1000
1000
SET
SET
= 500k,
6907fa
SET