LTC2242IUP-12 Linear Technology, LTC2242IUP-12 Datasheet - Page 16

• Manufacturer Part Number: LTC2242IUP-12
• Description: IC,A/D CONVERTER,SINGLE,12-BIT,CMOS,LLCC,64PIN
• Manufacturer: Linear Technology

APPLICATIONS INFORMATION
LTC2242-12
driver circuit. The V
close to the ADC with a 2.2μF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the dy-
namic performance of the LTC2242-12 can be infl uenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can infl uence SFDR. At the falling edge of ENC, the
sample-and-hold circuit will connect the 2pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when ENC rises, holding the
sampled input on the sampling capacitor. Ideally the
input circuitry should be fast enough to fully charge the
sampling capacitor during the sampling period 1/(2f
however, this is not always possible and the incomplete
settling may degrade the SFDR. The sampling glitch has
been designed to be as linear as possible to minimize the
effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2242-12 being driven by an RF
transformer with a center tapped secondary. The secondary
center tap is DC biased with V
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen
by the ADC does not exceed 100Ω for each ADC input.
A disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Figure 4 demonstrates the use of a differential amplifi er to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
16
CM
pin must be bypassed to ground
CM
, setting the ADC input
S
);
bandwidth of most op amps will limit the SFDR at high
input frequencies.
Figure 5 shows a capacitively-coupled input circuit. The im-
pedance seen by the analog inputs should be matched.
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from
ANALOG
INPUT
ANALOG
ANALOG
INPUT
0.1μF
Figure 4. Differential Drive with an Amplifi er
INPUT
0.1μF
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 5. Capacitively-Coupled Drive
0.1μF
0.1μF
DIFFERENTIAL
HIGH SPEED
+
CM
–
AMPLIFIER
1:1
T1
+
–
100Ω
25Ω
25Ω
50Ω
25Ω
25Ω
100Ω
3pF
25Ω
25Ω
0.1μF
10Ω
25Ω
25Ω
3pF
12pF
2.2μF
12pF
2.2μF
2.2μF
12pF
V
A
A
A
A
V
A
A
A
A
CM
V
IN
IN
IN
IN
A
A
A
A
IN
IN
IN
IN
CM
CM
IN
IN
IN
IN
+
+
–
–
+
+
–
–
+
+
–
–
LTC2242-12
LTC2242-12
LTC2242-12
224212 F05
224212 F04
224212 F03
224212fb