CYII5FM1300AB-QWC Cypress Semiconductor Corp, CYII5FM1300AB-QWC Datasheet
CYII5FM1300AB-QWC
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CYII5FM1300AB-QWC Summary of contents
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... Ordering Information See “Ordering Code Information” on page 33 for more infromation. Marketing Part Number CYII5SM1300AB-QDC CYII5SM1300AB-QWC CYII5SC1300AB-QDC CYII5FM1300AB-QDC CYII5SM1300-EVAL CYII5SC1300-EVAL CYII5FM1300-EVAL Cypress Semiconductor Corporation Document #: 38-05710 Rev. *G Description The IBIS5-B-1300 is a solid state CMOS image sensor that integrates the functionality of complete analog image acquisition, digitizer, and digital signal processing system on a single chip ...
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Contents Features ...............................................................................1 Applications ........................................................................1 Description ..........................................................................1 Ordering Information ..........................................................1 Contents ..............................................................................2 Specifications .....................................................................3 General Specifications. .................................................3 Electrical Specifications .................................................4 Architecture and Operation ...............................................5 Floor Plan ......................................................................5 Pixel ...............................................................................6 Image Core Operation ...................................................9 X-Addressing ...............................................................11 Y-addressing ...............................................................11 Output Amplifier ...........................................................12 ...
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Specifications Key Specifications Table 1. General Specifications Parameter Specifications Active pixels 1280 (H) × 1024 (V) Pixel size 6.7 µm × 6.7µm Master Clock 40 Mhz Shutter type Global and Rolling Shutter Frame rate 27 fps at full frame Windowing ...
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Electrical Specifications Recommended Operating Conditions Table 5. Recommended Operating Conditions Parameter Description VDDH Voltage on HOLD switches. VDDR_LEFT Highest reset voltage. VDDC Pixel core voltage. VDDA Analog supply voltage of the image core. VDDD Digital supply voltage of the image ...
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Architecture and Operation This section presents detailed information about the most important sensor blocks Figure 2. Block Diagram of IBIS5-B-1300 Image Sensor Pixel Y-left addressing Column amplifiers Floor Plan Figure 2 shows the architecture of the IBIS5-B-1300 image sensor. It ...
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Pixel A description of the pixel architecture and the color filter array follows. Architecture The pixel architecture used in the IBIS5-B-1300 is a 4-transistor pixel as shown in Figure 3. Implement the pixel using the high fill factor technique as ...
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... IBIS5-B-1300 (CYII5SM1300AB) and the IBIS-5-BE-1300 (CYII5FM1300AB). The curve is measured directly on the pixels. It includes effects of non-sensitive areas in the pixel, for example, interconnection lines. The sensor is light sensitive between 400 and 1000 nm. The peak 30%, approximately around 650 nm ...
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... The resulting voltage-electron curve is independent of any parameters (integration time, and others). The voltage to electrons conversion gain is 17.6 µV/electron. IBIS5-BE-1300 (CYII5FM1300AB) The IBIS5-BE-1300 is processed on a thicker epitaxial Si layer featuring a superb sensitivity in the NIR (Near Infra Red) wavelengths (700– ...
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Image Core Operation Image Core Operation and Signalling Figure functional representation of the image core without sub-sampling and column/row swapping circuits. Most of the signals involved are not available from the outside because they are generated by ...
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Global Shutter Supply Considerations The recommended supply voltage settings listed in used when the IBIS5-B-1300 sensor is in global shutter mode only. Table 8. Global Shutter Recommended Supply Settings Parameter Description VDDH Voltage on HOLD switches. VDDR_LEFT Highest reset voltage. ...
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X-Addressing Because of the high pixel rate, the X-shift register selects two columns at a time for readout runs at half the system clock speed. All even columns are connected to bus A; all odd columns to bus ...
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Output Amplifier Architecture and Settings The output amplifier stage is user programmable for gain and offset level. Gain is controlled by 4-bit wide word; offset by a 7-bit wide word. Gain settings are on an exponential scale. Offset is controlled ...
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Analog to Digital Converter The IBIS5-B-1300 has a 10-bit flash analog digital converter running nominally at 40 Msamples/s. The ADC is electrically separated from the image sensor. Tie the input of the ADC (ADC_IN; pin 69) externally to the output ...
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Non-linear and Linear Conversion Mode—’gamma’ Correction Figure 15 shows the ADC transfer characteristic. The non-linear (exponential) ADC conversion is intended for gamma-correction of the images. It increases contrast in dark areas and reduces contrast in bright areas. The non-linear transfer ...
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Electronic Shutter Types The IBIS5-B-1300 has two different shutter types: a rolling (curtain) shutter and a snapshot (synchronous) shutter. Rolling (Curtain) Shutter The name is due to the fact that the effect is similar to a curtain shutter of a ...
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Table 15. Internal Registers Register Bit 0 (0000) 11:0 SEQUENCER register 0 SHUTTER_TYPE 1 FRAME_CAL_MODE 2 LINE_CAL_MODE 3 CONT_CHARGE 4 GRAN_X_SEQ_LSB 5 GRAN_X_SEQ_MSB 6 GRAN_SS_SEQ_LSB 7 GRAN_SS_SEQ_MSB 8 KNEEPOINT_LSB 9 KNEEPOINT_MSB 10 KNEEPOINT_ENABLE 11 VDDR_RIGHT_EXT 1 (0001) 11:0 NROF_PIXELS 2 ...
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Table 15. Internal Registers (continued) Register Bit 9 (1001) 6:0 DACRAW_REG 10 (1010) 6:0 DACFINE_REG 11 (1011) 2:0 ADC register 0 TRISTATE_OUT 1 GAMMA 2 BIT_INV 12 (1100) Reserved 13 (1101) Reserved 14 (1110) Reserved 15 (1111) Reserved Detailed Description ...
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In normal (single slope) mode the pixel reset is controlled from the left side of the image core using the voltage applied on pin VDDR_LEFT as pixel reset voltage. In multiple slope operation, apply one or more variable pixel reset ...
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The actual integration time is given by Tint Integration time [# lines] = NROF_LINES register – INT_TIME register. Tint Integration time [# lines] = NROF_LINES register – INT_TIME register. X_REG Register (10:0) The X_REG register determines the start position of ...
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Serial 3-Wire Interface The serial 3-wire interface (or serial-to-parallel Interface) uses a serial input to shift the data in the register buffer. When the complete data word is shifted into the register buffer the data word is loaded into the ...
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Figure 20 shows a recommended schematic for generating the basic signals and to avoid any timing problems Figure 20. .Recommended Schematic for Generating Basic Signals SYS_CLOCK_N Figure 21. Relative Timing of the 5 Sequencer Control Signal Global Shutter: Single Slope ...
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NROF_PIXELS register (after a complete row read out). T —LAST_LINE goes high when the line counter reaches the 3 value loaded in the NROF_LINES register and stays high for one ...
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Global Shutter: Multiple Slope Integration Use up to four different pixel reset voltages during multiple slope operation in synchronous shutter mode. This is done by uploading new values KNEEPOINT_MSB/LSB/ENABLE before a new SS_START pulse is applied. Set bit KNEEPOINT_ENABLE high ...
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Rolling Shutter Operation The integration of the light in the image sensor is done during readout of the other lines. The only difference with synchronous shutter is that the TIME_OUT pin is used to indicate when the Y_SYNC pulse for ...
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Windowing in Y-direction Reapply the Y_START pulse after loading a new Y-pointer value into the YL_REG and YR_REG registers to load a new Y-pointer into the Y-shift-register. Initialization (Start-Up Behavior) To avoid any high current consumption at start-up, apply the ...
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Package Information Pin List The IBIS5-B-1300 image sensor is packaged in a leadless ceramic carrier (LCC package). There are 84 pins in total. [8, 9, 10] Table 26. Pin List Pin Pin Name Pin Type 1 P_DATA<8> Input 2 P_WR ...
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Table 26. Pin List (continued) Pin Pin Name Pin Type Notes 8. You can connect all pins with the same name together. 9. All digital input are active high (unless mentioned otherwise). 10. Tie all digital inputs ...
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Table 26. Pin List (continued) Pin Pin Name Pin Type 63 ADC_OUT<5> Output 64 ADC_OUT<4> Output 65 ADC_OUT<3> Output 66 ADC_OUT<2> Output 67 ADC_OUT<1> Output 68 ADC_OUT<0> Output 69 ADC_IN Input 70 ADC_CMD Input 71 ADC_VDDD Supply ...
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Pad position and Packaging Bare Die The IBIS5-B-1300 image sensor has 84 pins, 21 pins on every edge. The die size from pad-edge to pad-edge (without scribe-line) is: 10156.5 µm (x) by 9297.25 µm (y). Scribe lines take about 100 ...
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Package Drawing with Glass Document #: 38-05710 Rev. *G CYII5SM1300AB Page ...
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Table 27. Side View Dimensions (refer to on page 30). Dimension Description A Glass (thickness) - mono B Cavity (depth) C Die - Si (thickness) - mono D Bottom layer (thickness) E Die attach-bondline (thickness) F Glass attach-bondline (thickness) G ...
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Glass Lid The IBIS5-B-1300 image sensor uses a glass lid without any coatings. lid. As seen in Figure 31, the sensor does not use infrared attenuating color filter glass. You must provide a filter in the optical path when using ...
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Ordering Code Information Cypress Prefix I=Image Sensors IBIS5 S=Standard Process F=Thicker Epi M=Mono, C=Color Appendix A: IBIS5 Demo Kit For evaluating purposes an IBIS5 demo kit is available. The kit consists of a high speed digital board (mother board) along ...
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... Minor ECN to correct copyright year 04/01/10 Removed reference to I2C, IBIS5-A. Updated Figure 23, Added dynamic currents to Table 26. Updated Appendix A. Added handling and limited warranty statement. 10/12/2010 Removed MPN: CYII5FM1300AB-QWC Reformatted and edited section Filter Arrangement of Pixels” IBIS5-B-color” on page 6, new section “ ...