RF2051TR7 RFMD, RF2051TR7 Datasheet - Page 22

• Manufacturer Part Number: RF2051TR7
• Description: IC RF MIXER PLL/VCO 32-QFN
• Manufacturer: RFMD

Specifications of RF2051TR7

• Rf Type: UHF, VHF
• Frequency: 30MHz ~ 2.5GHz
• Number Of Mixers: 2
• Gain: -2dB
• Noise Figure: 12dB
• Secondary Attributes: Up/Down Converter
• Current - Supply: 75mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 689-1095-2

RF2051
Setting The Operating Frequency
Setting the operating frequency of the device requires a number of registers to be programmed.
A total of four registers must be programmed to set the device operating frequency for each path within the device. This will
take 5.2us for each path at maximum clock speed.
To change the frequency of the VCO it will be necessary to repeat these operations. However, if the frequency shift is small it
may not be necessary to reprogram the VCOSEL and LODIV bits reducing the register writes to three per path.
For an example on how to determine the integer and fractional parts of the synthesizer PLL division ratio please refer to the
detailed description of the PLL on page 12.
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3
P1_NUM_MSB,
P2_NUM_MSB
P1_NUM_LSB,
P2_NUM_LSB,
P1_LODIV and
Set operating
programmed
P1_VCOSEL,
P2_VCOSEL,
P1_CT_DEF,
P1_N, P2_N
frequencies
P2_CT_DEF
Frequency
P2_LODIV
Program
Program
Program
Program
When programming the operating frequency it is
necessary to select the appropriate VCO and LODIV
values. The P1_VCOSEL and P1_LODIV bits are
located in the PLL1x0 register and the corresponding
P2 bits in the PLL2x0 register.
If the LO frequency is above 2GHz the LO path current
(CFG5) should be set to 0xC
The integer part of the PLL division ratio is
programmed into the PLL1x3 and PLL2x3 registers
according to the required synthesizer path.
The MSB of the fractional part of the synthesizer PLL
divider value is programmed into the PLL1x1 and
PLL2x1 registers.
The LSB of the fractional part of the synthesizer PLL
divider value is programmed into the PLL1x2 and
PLL2x2 registers together with the CT_CAL bits if fast
frequency switching is required.
(Depending on required frequency resolution and
coarse tune settings this may not be required.)
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DS100630