CY7C006A-20AXCT Cypress Semiconductor Corp, CY7C006A-20AXCT Datasheet - Page 12

• Manufacturer Part Number: CY7C006A-20AXCT
• Description: CY7C006A-20AXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C006A-20AXCT

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 128K (16K x 8)
• Speed: 20ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Document Number: 38-06045 Rev. *F
Write Cycle No. 1: R/W Controlled Timing
Write Cycle No. 2: CE Controlled Timing
Notes
31. R/W or CE must be HIGH during all address transitions.
32. A write occurs during the overlap (t
33. t
34. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
35. To access RAM, CE = V
36. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
37. During this period, the I/O pins are in the output state, and input signals must not be applied.
38. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
CE
to be placed on the bus for the required t
as short as the specified t
HA
[35]
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
[35]
R/W
R/W
OE
IL
PWE
, SEM = V
.
t
t
SA
SA
NOTE 37
(continued)
SCE
IH
.
or t
SD
PWE
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
) of a LOW CE or SEM.
t
HZWE
[36]
[31, 32, 33, 38]
[31, 32, 33, 34]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[34]
t
t
SD
SD
PWE
or (t
HZWE
t
t
HA
HA
t
t
+ t
HD
HD
t
SD
LZWE
) to allow the I/O drivers to turn off and data
CY7C006A/CY7C007A
CY7C016A/CY7C017A
t
HZOE
[36]
NOTE 37
Page 12 of 22
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