CY62128ELL-55ZAXET Cypress Semiconductor Corp, CY62128ELL-55ZAXET Datasheet

CY62128ELL-55ZAXET

CY62128ELL-55ZAXET

Manufacturer Part Number
CY62128ELL-55ZAXET
Description
CY62128ELL-55ZAXET
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62128ELL-55ZAXET

Format - Memory
RAM
Memory Type
SRAM
Memory Size
1M (128K x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Package / Case
32-sTSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
1-Mbit (128K x 8) Static RAM
Features
Cypress Semiconductor Corporation
Document #: 38-05485 Rev. *H
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at
Logic Block Diagram
Very high speed: 45 ns
Temperature ranges
Voltage range: 4.5V to 5.5V
Pin compatible with CY62128B
Ultra low standby power
Ultra low active power
Easy memory expansion with CE
Automatic power down when deselected
CMOS for optimum speed and power
Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC, and
32-pin TSOP I packages
Industrial: –40°C to +85°C
Automotive-A: –40°C to +85°C
Automotive-E: –40°C to +125°C
Typical standby current: 1 A
Maximum standby current: 4 A (Industrial)
Typical active current: 1.3 mA at f = 1 MHz
CE 1
CE 2
WE
OE
1
, CE
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
A 8
A 9
A 10
A 11
2,
and OE features
198 Champion Court
COLUMN DECODER
INPUT BUFFER
128K x 8
ARRAY
Functional Description
The CY62128E
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99 percent when deselected (CE
eight input and output pins (I/O
high impedance state when the device is deselected (CE
or CE
operation is in progress (CE
To write to the device, take Chip Enable (CE
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
on the address pins (A
To read from the device, take Chip Enable (CE
HIGH) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
POWER
DOWN
1-Mbit (128K x 8) Static RAM
2
LOW), the outputs are disabled (OE HIGH), or a write
0
through I/O
San Jose
[1]
http://www.cypress.com.
is a high performance CMOS static RAM
7
,
) is then written into the location specified
0
CA 95134-1709
through A
1
LOW and CE
0
through I/O
CY62128E MoBL
16
Revised December 17, 2010
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
).
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1
0
1
2
3
4
5
6
7
HIGH or CE
2
HIGH and WE LOW)
7
1
) are placed in a
LOW and CE
1
LOW and CE
) in portable
408-943-2600
2
LOW). The
1
HIGH
2
®
2
[+] Feedback

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CY62128ELL-55ZAXET Summary of contents

Page 1

... Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at Cypress Semiconductor Corporation Document #: 38-05485 Rev. *H 1-Mbit (128K x 8) Static RAM Functional Description The CY62128E organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ ...

Page 2

Contents Pin Configuration .............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance........................................................... 5 AC Test Loads and Waveform ......................................... 5 Data Retention Characteristics ....................................... 5 Data ...

Page 3

... V CC Min CY62128ELL Ind’l/Auto-A 4.5 CY62128ELL Auto-E 4.5 Notes 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured When used with a 100 pF capacitive load and resistive loads as shown on page 4, access times Document #: 38-05485 Rev ...

Page 4

... Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05485 Rev. *H Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current..................................................... > 200 mA Operating Range Device + 0.5V) CC(max) CY62128ELL + 0.5V) CC(max) + 0.5V) CC(max (Ind’l/Auto-A) Test Conditions [3] Min Typ 2 ...

Page 5

Thermal Resistance [9] Parameter Description  Thermal Resistance Still Air, soldered × 4.5 inch, JA (Junction to Ambient) two-layer printed circuit board  Thermal Resistance JC (Junction to Case) AC Test Loads and Waveform ...

Page 6

Switching Characteristics (Over the Operating Range) Parameter Description Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW and CE ACE LOW to Data ...

Page 7

Switching Waveforms Figure 1. Read Cycle 1 (Address Transition Controlled) ADDRESS DATA OUT PREVIOUS DATA VALID Figure 2. Read Cycle No. 2 (OE Controlled) ADDRESS CE t ACE OE t LZOE HIGH IMPEDANCE DATA OUT t LZCE ...

Page 8

Switching Waveforms (continued) Figure 4. Write Cycle No. 2 (CE1 or CE2 Controlled) ADDRESS CE WE DATA I/O Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS NOTE 28 DATA I/O t HZWE Notes ...

Page 9

Truth Table [29 [29 Note 29. The ‘X’ (Don’t care) state for the Chip ...

Page 10

... Ordering Information Speed Ordering Code (ns) 45 CY62128ELL-45SXI CY62128ELL-45ZAXI CY62128ELL-45ZXI 45 CY62128ELL-45SXA CY62128ELL-45ZXA 55 CY62128ELL-55SXE CY62128ELL-55ZAXE Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions E V30 LL -xx xxx CY 621 2 8 Document #: 38-05485 Rev. *H Package Package Type Diagram 51-85081 32-pin 450-Mil SOIC (Pb-free) ...

Page 11

Package Diagrams Figure 6. 32-pin (450 Mil) Molded SOIC (51-85081) Document #: 38-05485 Rev. *H ® CY62128E MoBL 51-85081-*C Page [+] Feedback ...

Page 12

Figure 7. 32-pin Shrunk Thin Small Outline Package (8 x 13.4 mm) (51-85094) Figure 8. 32-pin Thin Small Outline Package Type mm) (51-85056) Document #: 38-05485 Rev. *H ® CY62128E MoBL 51-85094-*E 51-85056-*E Page 12 of ...

Page 13

Document History Page ® Document Title: CY62128E MoBL 1-Mbit (128K x 8) Static RAM Document Number: 38-05485 Submission Rev. ECN No. Date ** 203120 See ECN *A 299472 See ECN *B 461631 See ECN *C 464721 See ECN *D 563144 ...

Page 14

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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