CS8406-CZZR Cirrus Logic Inc, CS8406-CZZR Datasheet - Page 27

IC,Digital Audio Transmitter,CMOS,TSSOP,28PIN,PLASTIC

CS8406-CZZR

Manufacturer Part Number
CS8406-CZZR
Description
IC,Digital Audio Transmitter,CMOS,TSSOP,28PIN,PLASTIC
Manufacturer
Cirrus Logic Inc
Type
Digital Audio Interface Transmitterr
Datasheets

Specifications of CS8406-CZZR

Applications
Automotive Audio
Mounting Type
Surface Mount
Package / Case
28-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1017 - BOARD EVAL FOR CS8416 RCVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4266681

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS8406-CZZR
Manufacturer:
KINGBRIGHT
Quantity:
2 000
Part Number:
CS8406-CZZR
0
DS580F4
10.HARDWARE MODE
The CS8406 has a Hardware Mode that allows the use of the device without a microcontroller. Hardware Mode is
selected by connecting the H/S pin to VL. The flexibility of the CS8406 is necessarily limited in Hardware Mode.
Various pins change function as described in the Hardware Mode pin description section.
The Hardware Mode data flow is shown in
ed to the AES3 transmitter.
10.1
Channel Status, User and Validity Data
The transmitted channel status, user and validity data can be input in two methods, determined by the state
of the CEN pin. Mode A is selected when the CEN pin is low. In Mode A, the user bit data and the validity
bit are input through the U and V pins, clocked by both edges of ILRCK. The channel status data is derived
from the state of the COPY/C, ORIG, EMPH, and AUDIO pins.
pins map to channel status bits. In Consumer Mode, the transmitted category code is set to General (00h).
Mode B is selected when the CEN pin is high. In Mode B, the channel status, user data bits and the validity
bit are input serially through the COPY/C, U and V pins. Data is clocked into these pins at both edges of
ILRCK.
ILRCK
ISCLK
SDIN
Figure 9
Power supply pins are omitted from this diagram.
Please refer to the Typical Connection Diagram for hook-up details.
APMS
shows the timing requirements.
SFMT1 SFMT0
Serial
Audio
Input
RST
Figure 13. Hardware Mode Data Flow
Figure
13. Audio data is input through the serial audio input port and rout-
VL
H/S
COPY/C ORIG EMPH AUDIO
C, U, V Data Buffer
Table 2
shows how the COPY/C and ORIG
Output
Clock
Source
AES3
Encoder
& Tx
OMCK
TCBLD
TXP
TXN
CEN
U
V
TCBL
CS8406
27

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