CS5532-BSZR Cirrus Logic Inc, CS5532-BSZR Datasheet
CS5532-BSZR
Specifications of CS5532-BSZR
Available stocks
Related parts for CS5532-BSZR
CS5532-BSZR Summary of contents
Page 1
... ADCs Ultra-low-noise PGIA with General Description The CS5532/34 are highly integrated ∆Σ Analog-to-Digi- tal Converters (ADCs) which use charge-balance techniques to achieve 24-bit performance. The ADCs are optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications ...
Page 2
... Conversion Output Coding ..............................................................................36 2.9. Digital Filter ......................................................................................................38 2.10. Clock Generator ...............................................................................................39 2.11. Power Supply Arrangements ...........................................................................39 2.12. Getting Started ................................................................................................43 2.13. PCB Layout .....................................................................................................43 3. PIN DESCRIPTIONS ...............................................................................................44 4. SPECIFICATION DEFINITIONS ...............................................................................46 5. ORDERING INFORMATION .....................................................................................47 6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ..............47 7. PACKAGE DRAWINGS ...........................................................................................48 2 CS5532/34-BS DS755F3 ...
Page 3
... Figure 17. 120 Sps Filter Magnitude Plot to 120 Hz ............................................................... 38 Figure 19. Z-Transforms of Digital Filters................................................................................ 38 Figure 20. On-chip Oscillator Model........................................................................................ 39 Figure 21. CS5532 Configured with a Single +5 V Supply ..................................................... 40 Figure 22. CS5532 Configured with ±2.5 V Analog Supplies.................................................. 41 Figure 23. CS5532 Configured with ±3 V Analog Supplies..................................................... 41 Figure 24. CS5532 Configured for Thermocouple Measurement ........................................... 42 Figure 25 ...
Page 4
... G is the amplifier gain setting. 4. Drift over specified temperature range after calibration at power- °C. 4 Min Typ ±0.0007 - 24 ±16 - ±32 - (Notes 3 and 4) - 640 ±8 - ±16 - (Note CS5532/34-BS Max Unit ±0.0015 % Bits ±32 LSB 24 ±64 LSB 24 - nV/°C ±31 ppm ±62 ppm - ppm/°C ...
Page 5
... VA+ or VA-. This is due to the rough charge buffer being saturated under these conditions. DS755F3 (Continued) Gain = 1 Gain = 16, 32, 64 (Note 5) Gain = 1 (Note 6, 7) Gain = 16, 32, 64 Gain = 1 Gain = 16, 32, 64 dc, Gain = 1 dc, Gain = 64 50 (VREF+) - (VREF-) (Note 50 Bipolar/Unipolar Mode Bipolar Mode Unipolar Mode CS5532/34-BS Min Typ Max Unit VA- - VA+ VA- + 0.7 - VA 1200 - - 200 - pA/√Hz - ...
Page 6
... All outputs unloaded. All input CMOS levels. 9. Power is specified when the instrumentation amplifier (Gain ≥ on. Analog supply current is reduced by approximately 1/2 when the instrumentation amplifier is off (Gain = 1). 10. Tested with 100 mV change on VA+ or VA-. 6 (Continued) Min (Notes 8 and 9) (Note 10) CS5532/34-BS Max Typ Unit - 0 ...
Page 7
... Instrumentation Amplifier Gain x64 x32 x16 CS5532/34- 140 59 103 198 514 1020 2050 730 1450 2900 1030 2060 4110 1810 3620 7230 10800 21500 43000 ...
Page 8
... Symbol All Pins Except SCLK V IH SCLK All Pins Except SCLK V IL SCLK = -1 out OH SDO -5.0 mA out = 1 out OL SDO 5.0 mA out out CS5532/34-BS Min Typ Max 0.6 VD+ - VD+ (VD+) - 0.45 - VD+ 0.0 - 0.8 0.0 0.6 (VA (VD (VA-) + 0.4 0.4 - ±1 ± ±10 - ...
Page 9
... Positive Digital VD+ Positive Analog VA+ Negative Analog VA- (Notes 24 and 25 OUT (Note 26) PDN VREF pins V INR AIN Pins V INA V IND T T stg CS5532/34-BS Ratio f MCLK/ 1/OWR 5/OWR + 3/OWR s sinc5 t 5/OWR s refers to the 3200 Sps (FRS = 1) or 3840 Sps Min Typ Max -0.3 - +6.0 -0 ...
Page 10
... MCLK (Note 28) t rise SCLK Any Digital Output (Note 28) t fall SCLK Any Digital Output (Note 29) t ost SCLK Pulse Width High t 1 Pulse Width Low CS5532/34-BS Min Typ Max Unit 1 4.9152 5 MHz 1.0 µ 100 µ 1.0 µ 100 µ ...
Page 11
... DS755F3 Figure 1. SDI Write Timing (Not to Scale Figure 2. SDO Read Timing (Not to Scale) CS5532/34- ...
Page 12
... Schmitt-trigger input on the serial clock (SCLK). 2.1. Analog Input Figure 3 illustrates a block diagram of the CS5532/34. The front end consists of a multiplexer, a unity gain coarse/fine charge input buffer, and a programmable-gain, chopper-stabilized instrumen- tation amplifier. The unity gain buffer is activated ...
Page 13
... Voltage Noise Density Performance Figure 5 illustrates the measured voltage noise density versus frequency from 0.025 CS5532-BS. The device was powered with ±2.5 V supplies, using 30 Sps OWR, the 64x gain range, bipolar mode, and with the input short bit enabled. ...
Page 14
... Each of the converters has 32-bit registers to func- tion as offset and gain calibration registers for each channel. The CS5532 has two offset and two gain calibration registers, the CS5534 has four offset and four gain calibration registers. These registers ...
Page 15
... System Initialization The CS5532/34 provide no power-on-reset func- tion. To initialize the ADCs, the user must perform a software reset by resetting the ADC’s serial port with the Serial Port Initialization sequence. This se- ...
Page 16
... The RS bit should be written back to logic 0 to complete the re- set cycle. After a system initialization or reset, the 16 CS5532/34-BS on-chip controller is initialized into command mode where it waits for a valid command (the first 8 bits written into the serial port are shifted into the command register) ...
Page 17
... These bits are used as pointers to the channel-setup registers. Either a single con- version or continuous conversions are performed on the channel setup register pointed to by these bits. Normal Conversion Self-Offset Calibration Self-Gain Calibration Reserved Reserved System-Offset Calibration System-Gain Calibration Reserved CS5532/34- RSB2 RSB1 RSB0 CC2 ...
Page 18
... These commands are used to access each offset register separately. CS1 - CS0 decode the registers accessed. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. CS[1:0] (Channel Select Bits) 00 Offset Register 1 01 Offset Register 2 10 Offset Register 3 (CS5534 only) 11 Offset Register 4 (CS5534 only CS1 CS0 R/W CS5532/34- DS755F3 ...
Page 19
... Channel-Setup Register 1 01 Channel-Setup Register 2 10 Channel-Setup Register 3 11 Channel-Setup Register 4 READ/WRITE CONFIGURATION REGISTER D7(MSB Function: These commands are used to read from or write to the configuration register. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. DS755F3 CS1 CS0 R CS1 CS0 R R/W CS5532/34- ...
Page 20
... CRSP0) in the channel-setup register. MC (Multiple Conversions) 0 Perform a single conversion. 1 Perform continuous conversions. CSRP [2:0] (Channel Setup Register Pointer Bits) 000 Setup 1 001 Setup 2 010 Setup 3 011 Setup 4 100 Setup 5 101 Setup 6 110 Setup 7 111 Setup CSRP1 CSRP0 CS5532/34- DS755F3 ...
Page 21
... Function: Part of the serial port re-initialization sequence. SYNC0 D7(MSB Function: End of the serial port re-initialization sequence. NULL D7(MSB Function: This command is used to clear a port flag and keep the converter in the continuous conversion mode. DS755F3 CSRP1 CSRP0 CS5532/34- CC2 CC1 CC0 ...
Page 22
... Serial Port Interface The CS5532/34’s serial interface consists of four control lines: CS, SDI, SDO, SCLK. Figure 7 de- tails the command and data word timing. CS, Chip Select, is the control line which enables access to the serial port. If the CS pin is tied low, the port can function as a three wire interface. ...
Page 23
... In the CS5532, there are two gain and offset registers, and in the CS5534, there are four gain and offset registers. There are four channel setup registers in both devices ...
Page 24
... VRS setting. As the models show, the reference includes a coarse/fine charge 24 CS5532/34-BS buffer which reduces the dynamic current demand of the external reference. The reference’s input buffer is designed to accom- modate rail-to-rail (common-mode plus signal) in- put voltages ...
Page 25
... Sps when using a 4.9152 MHz clock. When using other clock frequencies, these selectable word rates will scale linearly with the clock frequency that is used. CS5532/34-BS φ Fine 1 φ Coarse 2 ...
Page 26
... Calibration registers used are based on the CS1-CS0 bits of the referenced Setup. 1 Calibration registers used are based on the OG1-OG0 bits of the referenced Setup. 26 D26 D25 D24 D23 IS GB VRS A1 A0 D10 CS5532/34-BS D22 D21 D20 D19 D18 OLS NU OGS FRS D17 D16 ...
Page 27
... Channel Setup Registers. Each 32-bit CSR is individually accessible and contains two 16-bit Setups example, to con- figure Setup 1 in the CS5532/34 with the write in- dividual channel-setup register command (0x05 hexadecimal), bits CSR 1 contains the information for Setup 1 and bits contain the information for Setup 2 ...
Page 28
... U/B D10 WR3 WR2 WR1 WR0 U/B WR (FRS = 1) 100 Sps 50 Sps 25 Sps 12.5 Sps 6.25 Sps 3200 Sps 1600 Sps 800 Sps 400 Sps 200 Sps CS5532/34-BS D21 D20 D19 D18 D17 OL1 OL0 DT OCD OG1 OL1 OL0 DT OCD OG1 DS755F3 ...
Page 29
... CS0 bits of the Setup) will be used. 00 Use offset and gain register from physical channel 1 01 Use offset and gain register from physical channel 2 10 Use offset and gain register from physical channel 3 11 Use offset and gain register from physical channel 4 DS755F3 CS5532/34-BS 29 ...
Page 30
... Calibration Calibration is used to set the zero and gain slope of the ADC’s transfer function. The CS5532/34 offer both self calibration and system calibration. Note: After the ADCs are reset, they are functional and can perform measurements without being calibrated (remember that the VRS bit in the configuration register must be properly configured) ...
Page 31
... To calibrate all the channels, additional calibration commands are necessary. 2.5.5. Self Calibration The CS5532/34 offer both self-offset and self-gain calibrations. For the self calibration of offset, the converters internally tie the inputs of the 1x ampli- fier together and routes them to the AIN- pin as shown in Figure 11 ...
Page 32
... Note that accessing the ADC’s serial port before a calibration has finished may re- sult in the loss of synchronization between the mi- AIN+ + AIN- _ VREF+ + Reference - VREF- Figure 12. Self Calibration of Gain External Connections + AIN+ Full Scale + - - AIN Figure 14. System Calibration of Gain CS5532/34-BS OPEN + + XGAIN - - OPEN CLOSED CLOSED + + XGAIN - - DS755F3 ...
Page 33
... Setup (see Section 2.3.7 for more details). If factory calibration of the user’s system is per- formed using the system calibration capabilities of the CS5532/34, the offset and gain register contents can be read by the system microcontroller and re- corded in non-volatile memory. These same cali- ...
Page 34
... The (FRS = 1) clock ambiguity is due to internal syn- chronization between the SCLK input and the os- cillator. Note: CS5532/34-BS 8 (FRS = 0) or ± When changing channels, or after performing calibrations and/or single conversions, the user must ignore the first three (for OWRs less than 3200 Sps, MCLK = 4.9152 MHz) or first five (for OWR ≥ ...
Page 35
... Register is set to ‘0’. The command issued is 4 ‘10011001’. This instructs the converter to perform 5 a self offset calibration referencing Setup 4 6 (CSRP2 - CSRP0 = ‘011’). In this example, Setup 7 4 points to physical channel 2. After the command 8 is received and decoded, the ADC performs a self CS5532/34-BS 35 ...
Page 36
... Using Multiple ADCs Synchronously Some applications require synchronous data out- puts from multiple ADCs converting different ana- log channels. Multiple CS5532/34 parts can be synchronized in a single system by using the fol- lowing guidelines: 1) All of the ADCs in the system must be operated from the same oscillator source ...
Page 37
... Table 4. Output Coding for 24-bit CS5532 and CS5534 Unipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 LSB VFS/2-0.5 LSB +0.5 LSB <(+0.5 LSB) 2.8.1. Conversion Data Output Descriptions D31(MSB) D30 D29 D28 D27 MSB D15 D14 D13 D12 D11 Conversion Data Bits [31:8] These bits depict the latest output conversion ...
Page 38
... Digital Filter The CS5532/34 have linear phase digital filters which are programmed to achieve a range of output word rates (OWRs) as stated in the Channel-Setup Register Descriptions section. The ADCs use a 5 Sinc digital filter to output word rates at 3200 Sps and 3840 Sps (MCLK = 4.9152 MHz). Other out- ...
Page 39
... V. Figure 22 il- lustrates the CS5532 connected with ±2.5 V bipo- lar analog supplies and digital supply to measure ground referenced bipolar sig- nals. Figures 23 and 24 illustrate the CS5532 con- nected with ±3 V analog supplies and digital supply to measure ground referenced bipo- lar signals. ...
Page 40
... V Analog Supply - Figure 21. CS5532 Configured with a Single +5 V Supply 40 10 Ω 0.1 µ VA+ VD+ OSC2 18 VREF+ 17 VREF- 3 OSC1 CS5532 AIN1+ 2 AIN1- SDI 20 AIN2+ SDO 19 AIN2- SCLK DGND 6 16 CS5532/34-BS 0.1 µF Optional ...
Page 41
... V Analog Supply - -2.5 V Analog Supply Figure 22. CS5532 Configured with ±2.5 V Analog Supplies +3 V Analog Supply - -3 V Analog Supply Figure 23. CS5532 Configured with ±3 V Analog Supplies DS755F3 0.1 µ VA+ VD+ 18 OSC2 VREF+ 17 VREF- 3 OSC1 CS5532 AIN1+ 2 AIN1- SDI 20 AIN2+ SDO 19 AIN2- ...
Page 42
... V Analog Supply 2. Analog Supply Figure 24. CS5532 Configured for Thermocouple Measurement V+ ( Ω 0.1 µF 5 VA+ VD+ 1 AIN1+ OSC2 2 AIN1 CS5532 VREF+ 17 VREF- 20 AIN2+ Cold 19 AIN2- Junction DGND Figure 25. Bridge with Series Resistors CS5532/34-BS 0.1 µF 15 Optional 9 Clock Source 4.9152 MHz 10 OSC1 ...
Page 43
... To accommodate for this recommended that a software delay of approximately 20 ms start the processor’s ADC initialization code. Next, since the CS5532/34 do not provide a power-on-re- set function, the user must first initialize the ADC to a known state. This is accomplished by resetting the ADC’s serial port with the Serial Port Initializa- tion sequence ...
Page 44
... DIFFERENTIAL ANALOG INPUT VREF+ VOLTAGE REFERENCE INPUT VREF- VOLTAGE REFERENCE INPUT 6 19 VA+ DGND DIGITAL GROUND 7 18 VD+ VA- POSITIVE DIGITAL POWER CHIP SELECT SDI SERIAL DATA INPUT 10 15 SDO SERIAL DATA OUT OSC2 11 14 OSC1 SERIAL CLOCK INPUT SCLK 12 13 CS5532/34-BS DS755F3 ...
Page 45
... C1 Amplifier Capacitor Inputs. Connections for the instrumentation amplifier’s capacitor. Power Supply Connections VA+ - Positive Analog Power. Positive analog supply voltage. VD+ - Positive Digital Power. Positive digital supply voltage (nominally +3 V). VA- - Negative Analog Power. Negative analog supply voltage. DGND - Digital Ground. Digital Ground. DS755F3 CS5532/34-BS 45 ...
Page 46
... When in unipolar mode (U/B bit = 1). Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the AIN- pin). When in bipolar mode (U/B bit = 0). Units are in LSBs. 46 CS5532/34-BS DS755F3 ...
Page 47
... Peak Reflow Temp MSL Rating* 240 °C 260 °C 240 °C 260 °C CS5532/34-BS Package 20-pin 0.2" Plastic SSOP 20-pin 0.2" Plastic SSOP, Lead Free 24-pin 0.2" Plastic SSOP 24-pin 0.2" Plastic SSOP, Lead Free Max Floor Life ...
Page 48
... CS5532/34- ∝ END VIEW L NOTE MILLIMETERS MAX -- 2.13 0.25 1.88 0.38 2,3 7.50 1 8.20 5.60 1 0.69 1.03 0° ...
Page 49
... CS5532/34- ∝ END VIEW L NOTE MILLIMETERS MAX -- 2.13 0.25 1.88 0.38 2,3 8.50 1 8.20 5.60 1 0.69 1.03 0° ...
Page 50
... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. 50 CHANGES www.cirrus.com CS5532/34-BS DS755F3 ...