CS5368-DQZR Cirrus Logic Inc, CS5368-DQZR Datasheet - Page 23

• Manufacturer Part Number: CS5368-DQZR
• Description: IC,A/D CONVERTER,OCTAL,24-BIT,QFP,48PIN
• Manufacturer: Cirrus Logic Inc

DS624A1
4.6.3 Synchronization of Multiple Devices
4.6.4 Sample Rate Ranges
4.6.5 Using M1 and M0 to Set Sampling Parameters
To ensure synchronous sampling in applications where multiple ADCs are used, the MCLK and LRCK
must be the same for all of the CS5368s in the system. If only one Master clock source is needed, one
solution is to place one CS5368 in Master mode, and slave all of the other devices to the one master. If
multiple Master clock sources are needed, a possible solution would be to supply all clocks from the same
external source and time the CS5368 reset de-assertion with the falling edge of MCLK. This will ensure
that all converters begin sampling on the same clock edge.
Supported sampling rates are 2 kHz-216 kHz divided into three ranges: 2 kHz-54 kHz, 54 kHz-108 kHz,
and 108 kHz-216 kHz. These sampling speed modes are called Single-Speed Mode, Double-Speed
Mode and Quad-Speed Mode (SSM, DSM, QSM), respectively.
The Master/Slave operation and the sample rate range are controlled through the settings of the M1 and
M0 pins in Stand-Alone Mode, or by the M[1] and M[0] bits in the Global Mode Control Register in Control-
Port Mode.
M1
0
0
1
1
ADC as
master
timing
M0
0
1
0
1
Figure 10. Master and Slave Clocking for a 32-Channel Application
SCLK
LRCK
CS5368
Master
Auto-Detected Speed Slave Mode
Quadruple-Speed Master Mode
Double-Speed Master Mode
Single-Speed Master Mode
Controller
SCLK & LRCK/FS
Figure 9. Master Slave Clock Flow
Table 2. M1 and M0 Settings
Mode
CS5368
CS5368
CS5368
Slave1
Slave2
Slave3
ADC as
timing
slave
SCLK
LRCK
Frequency Range
108 kHz - 216 kHz
54 kHz - 108 kHz
2 kHz - 216 kHz
2 kHz - 54 kHz
Controller
CS5368
27