CS4398-CZZR Cirrus Logic Inc, CS4398-CZZR Datasheet - Page 38

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CS4398-CZZR

Manufacturer Part Number
CS4398-CZZR
Description
IC,D/A CONVERTER,DUAL,24-BIT,TSSOP,28PIN
Manufacturer
Cirrus Logic Inc
Datasheets

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0
38
7.9
7.9.1
7.9.2
7.9.3
7.9.4
Reserved Reserved Reserved Reserved STATIC_DSD INVALID_DSD
7
0
Misc. Control - Register 09h
Static DSD Detect (Static_DSD) Bit 3
Function:
When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected,
sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE
register.
When set to 0, this function is disabled.
Invalid DSD Detect (Invalid_DSD) Bit 2
Function:
When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if de-
tected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE
register.
When set to 0 (default), this function is disabled.
DSD Phase Modulation Mode Select (DSD_PM_mode) Bit 1
Function:
When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for phase modulation
mode. (See Figure 13 on page 24)
When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for phase modulation mode.
DSD Phase Modulation Mode Enable (DSD_PM_EN) Bit 0
Function:
When set to 1, DSD phase modulation input mode is enabled and the DSD_PM_MODE bit should be set
accordingly.
When set to 0 (default), this function is disabled (DSD normal mode).
6
0
0
5
4
0
1
3
2
0
DSD_PM_MODE DSD_PM_EN
1
0
CS4398
DS568F1
0
0

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