CS4350-DZZR Cirrus Logic Inc, CS4350-DZZR Datasheet - Page 22

• Manufacturer Part Number: CS4350-DZZR
• Description: IC 105dB 192kHz DAC W/PLL
• Manufacturer: Cirrus Logic Inc

Specifications of CS4350-DZZR

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 290mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1517 - BOARD EVAL FOR CS4350 DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22
4.6.2
4.7
4.7.1
4.7.2
4.7.3
Popguard Transient Control
The CS4350 uses a novel technique to minimize the effects of output transients during power-up and power-
down. This technology, when used with external DC-blocking capacitors in series with the audio outputs,
minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated
inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing the
appropriate DC-blocking capacitors.
Control Port Mode
1. Hold RST low until the power supply is stable and the left/right clock is fixed to the appropriate
2. Bring RST high. The device will remain in a low-power state with VQ low.
3. Perform a control port write to a valid register prior to the completion of approximately 512 LRCK
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs when
Power-Up
When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to GND.
Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quies-
cent voltage. Approximately 10,000 LRCK cycles later, the outputs reach V
This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quies-
cent voltage, minimizing audible power-up transients.
Power-Down
To prevent audible transients at power-down, the device must first enter its power-down state. When this
occurs, audio output ceases and the internal output buffers are disconnected from AOUTA and AOUTB.
In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly dis-
charge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready
for the next power-on.
Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge be-
fore turning on the power or exiting the power-down state. If full discharge does not occur, a transient will
occur when the audio outputs are initially clamped to GND. The time that the device must remain in the
power-down state is related to the value of the DC-blocking capacitance and the output load. For example,
with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.
frequency, as discussed in
will remain low, and VBIAS will be connected to VA.
cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in
Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1.
the Popguard is disabled. If the Popguard is enabled, see
power-up timing.
Section
4.2. In this state, the control port is reset to its default settings, VQ
Section 4.7
for a complete description of
Q
and audio output begins.
CS4350
DS691F1