CS4245-CQZR Cirrus Logic Inc, CS4245-CQZR Datasheet - Page 38

• Manufacturer Part Number: CS4245-CQZR
• Description: IC,Soundcard Circuits,QFP,48PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

38
4.13
SCL
SDA
START
Interrupts and Overflow
The CS4245 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may function as either an active high CMOS driver or an
active low open-drain driver (see
open-drain, the INT pin has no active pull-up transistor, allowing it to be used for wired-OR hook-ups with
multiple peripherals connected to the microcontroller interrupt input pin. In this configuration, an external
pull-up resistor must be placed on the INT pin for proper operation.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see
Status - Address 0Dh” on page
each source may be set to rising edge, falling edge, or level-sensitive. Combined with the option of level-
sensitive or edge-sensitive modes within the microcontroller, many different configurations are possible, de-
pending on the needs of the equipment designer.
The CS4245 also has a dedicated overflow output. The OVFL pin functions as active low open drain and
has no active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs an OR
of the ADCOverflow and ADCUnderflow conditions available in the Interrupt Status register; however, these
conditions do not need to be unmasked for proper operation of the OVFL pin.
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
0
1
Figure
CHIP ADDRESS (WRITE)
1
0
0
2
1
3
19, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
1 AD1 AD0 0
4
5
6
7
ACK
8
9
7
10 11
6
Figure 19. Control Port Timing, I²C Read
49). Each source may be masked off through mask register bits. In addition,
5
MAP BYTE
12 13 14 15
4
“Active High/Low (Bit 0)” on page
3
2
1
16
0
ACK
STOP
17 18
START
19
1
20 21 22 23 24
CHIP ADDRESS (READ)
0
0
1
1 AD1 AD0 1
25
26 27 28
49). When configured as active low
ACK
7
DATA
0
ACK
DATA +1
7
0
DATA + n
7
CS4245
0
ACK
NO
DS656F2
“Interrupt
STOP