CS2300P-DZZ Cirrus Logic Inc, CS2300P-DZZ Datasheet - Page 16

• Manufacturer Part Number: CS2300P-DZZ
• Description: IC General Purpose PLL LCO
• Manufacturer: Cirrus Logic Inc
• Type: Fanout Distribution, Fractional N Synthesizerr

Specifications of CS2300P-DZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1494 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16
5.5
User Defined Ratio R
Ratio 0
Ratio 1
Ratio 2
Ratio 3
PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.
The driver can be set to high-impedance with the M2 pin when the M2Config[1:0] global parameter is set to
either 000 or 010. The output from the PLL automatically drives a static low condition while the PLL is un-
locked (when the clock may be unreliable). This feature can be disabled by setting the ClkOutUnl global
parameter, however the state CLK_OUT may then be unreliable during an unlock condition.
ratio R
in
fractional-N value which controls the Frequency Synthesizer. The subscript ‘4’ indicates the modal param-
eters.
Referenced Control
Ratio
M[1:0]
LFRatioCfg
RModSel[1:0]
AutoRMod
Referenced Control
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 22
ClkOutDis
M2Config[2:0]........................“M2 Pin Configuration (M2Config[2:0])” on page 22
Figure 10
UD
PLL Output
M[1:0] pins
0-3................................“Ratio 0 - 3” on page 21
pins.............................“M1 and M0 Mode Pin Functionality” on page 17
EFF
..............................“M2 Configured as Output Disable” on page 18
.............................“Auto R-Modifier Enable (AutoRMod)” on page 21
Effective Ratio R
............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 22
, the final calculation used to determine the output to input clock ratio. The conceptual diagram
0
........................“R-Mod Selection (RModSel[1:0])” section on page 20
summarizes the features involved in the calculation of the ratio values used to generate the
Ratio Format
LFRatioCfg
12.20
20.12
EFF
2:1 Mux
0
1
ClkOutUnl
Parameter Definition
Parameter Definition
Modifier
Ratio
Figure 11. PLL Clock Output Options
AutoRMod
or M2 pin
Figure 10. Ratio Feature Summary
M2 pin
RModSel[1:0]
FsDet[1:0]
4
R-Mod
PLL Locked/Unlocked
Auto
Confidential Draft
2:1 Mux
0
1
4
Frequency Reference Clock
3/18/09
Fractional N Logic
Digital PLL &
(CLK_IN)
PLL Clock Output
PLLClkOut
M2Config[1:0] = 000, 010
Dynamic Ratio, ‘N’
M2 pin with
LCO
Synthesizer
Frequency
PLL Clock Output Pin
(CLK_OUT)
CS2300-OTP
DS844PP2
PLL Output