AM29F800BB-120EC Spansion Inc., AM29F800BB-120EC Datasheet

AM29F800BB-120EC

Manufacturer Part Number

AM29F800BB-120EC

Description

Flash Memory IC

Manufacturer

Spansion Inc.

Datasheets

1.AM29F800BT-90SC.pdf (44 pages)

2.AM29F800BB-90EI.pdf (44 pages)

3.AM29F800BT-90SC.pdf (43 pages)

4.AM29F800BB-90EE.pdf (45 pages)

Specifications of AM29F800BB-120EC

Memory Size

8Mbit

Memory Configuration

1M X 8 / 512K X 16

Ic Interface Type

Parallel

Access Time

120ns

No. Of Pins

Operating Temperature Range

0Â°C To +70Â°C

Termination Type

SMD

Memory Voltage, Vcc

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Download datasheet (2Mb)

Am29F800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 5.0 Volt-only, Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Single power supply operation

— 5.0 Volt-only operation for read, erase, and

— Minimizes system level requirements

Manufactured on 0.32 µm process technology

— Compatible with 0.5 µm Am29F800 device

High performance

— Access times as fast as 55 ns

Low power consumption (typical values at

5 MHz)

— 1 µA standby mode current

— 20 mA read current (byte mode)

— 28 mA read current (word mode)

— 30 mA program/erase current

Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

— One 8 Kword, two 4 Kword, one 16 Kword, and

— Supports full chip erase

— Sector Protection features:

— Sectors can be locked via programming

Top or bottom boot block configurations

available

program operations

fifteen 64 Kbyte sectors (byte mode)

fifteen 32 Kword sectors (word mode)

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

equipment

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

Embedded Algorithms

— Embedded Erase algorithm automatically

— Embedded Program algorithm automatically

Minimum 1,000,000 program/erase cycles per

sector guaranteed

20-year data retention at 125 C

— Reliable operation for the life of the system

Package option

— 48-pin TSOP

— 44-pin SO

— 48-ball FBGA

— Known Good Die (KGD)

Compatibility with JEDEC standards

— Pinout and software compatible with single-

— Superior inadvertent write protection

Data# Polling and toggle bits

— Provides a software method of detecting

Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

preprograms and erases the entire chip or any

combination of designated sectors

writes and verifies data at specified addresses

(see publication number 21631)

power-supply Flash

program or erase operation completion

program or erase cycle completion

or program data to, a sector that is not being

erased, then resumes the erase operation

array data

Publication# 21504

Issue Date: August 4, 2000

Rev: E Amendment/+1

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