ADV7180KCP32Z Analog Devices Inc, ADV7180KCP32Z Datasheet - Page 27

• Manufacturer Part Number: ADV7180KCP32Z
• Description: 10-bit 4x Oversampling SDTV Decoder
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7180KCP32Z

• Design Resources: Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
• Applications: Digital Cameras, Mobile Phones, Portable Video
• Voltage - Supply, Analog: 1.71 V ~ 1.89 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SRLS, Select Raw Lock Signal, Address 0x51[6]
Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits[1:0] in the Status 1 register).
See Figure 19.
•
•
Setting SRLS to 0 (default) selects the FREE_RUN signal.
Setting SRLS to 1 selects the TIME_WIN signal.
FSCLE, f
The FSCLE bit allows the user to choose whether the status of
the color subcarrier loop is taken into account when the overall
lock status is determined and presented via Bits[1:0] in the
Status 1 register. This bit must be set to 0 when operating the
ADV7180 in YPrPb component mode to generate a reliable
HLOCK status bit.
When FSCLE is set to 0 (default), only the overall lock status is
dependent on horizontal sync lock.
When FSCLE is set to 1, the overall lock status is dependent on
horizontal sync lock and f
CIL[2:0], Count Into Lock, Address 0x51[2:0]
CIL[2:0] determines the number of consecutive lines for which
the lock condition must be true before the system switches into
the locked state and reports this via Status 1[1:0]. The bit counts
the value in lines of video.
Table 25. CIL Function
CIL[2:0]
000
001
010
011
100 (default)
101
110
111
The TIME_WIN signal is based on a line-to-line evaluation
of the horizontal synchronization pulse of the incoming
video. It reacts quite quickly.
The FREE_RUN signal evaluates the properties of the
incoming video over several fields, taking vertical
synchronization information into account.
SC
Lock Enable, Address 0x51[7]
Number of Video Lines
1
2
5
10
100
500
1000
100,000
SC
lock.
Rev. F | Page 27 of 116
COL[2:0], Count Out of Lock, Address 0x51[5:3]
COL[2:0] determines the number of consecutive lines for which
the out-of-lock condition must be true before the system switches
into the unlocked state and reports this via Status 1[1:0]. It counts
the value in lines of video.
Table 26. COL Function
COL[2:0]
000
001
010
011
100 (default)
101
110
111
COLOR CONTROLS
These registers allow the user to control picture appearance,
including control of the active data in the event of video being
lost. These controls are independent of any other controls. For
instance, brightness control is independent of picture clamping,
although both controls affect the dc level of the signal.
CON[7:0], Contrast Adjust, Address 0x08[7:0]
This register allows the user to control contrast adjustment of
the picture.
Table 27. CON Function
CON[7:0]
0x80 (default)
0x00
0xFF
SD_SAT_Cb[7:0], SD Saturation Cb Channel,
Address 0xE3[7:0]
This register allows the user to control the gain of the Cb channel
only, which in turn adjusts the saturation of the picture.
Table 28. SD_SAT_Cb Function
SD_SAT_Cb[7:0]
0x80 (default)
0x00
0xFF
SD_SAT_Cr[7:0], SD Saturation Cr Channel,
Address 0xE4[7:0]
This register allows the user to control the gain of the Cr channel
only, which in turn adjusts the saturation of the picture.
Table 29. SD_SAT_Cr Function
SD_SAT_Cr[7:0]
0x80 (default)
0x00
0xFF
Number of Video Lines
1
2
5
10
100
500
1000
100,000
Description
Gain on Cr channel = 0 dB
Gain on Cr channel = −42 dB
Gain on Cr channel = +6 dB
Gain on Cb channel = 0 dB
Description
Gain on Cb channel = −42 dB
Gain on Cb channel = +6 dB
Description
Gain on luma channel = 1
Gain on luma channel = 0
Gain on luma channel = 2
ADV7180