ADSP-BF514BBCZ-4F4 Analog Devices Inc, ADSP-BF514BBCZ-4F4 Datasheet
ADSP-BF514BBCZ-4F4
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ADSP-BF514BBCZ-4F4 Summary of contents
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F FEATURES Up to 400 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Wide range of operating voltages ...
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... CSP_BGA Ball assignment ............................ 65 Outline Dimensions ................................................ 68 Surface-Mount Design .......................................... 69 Automotive Products .............................................. 70 Ordering Guide ..................................................... 70 Revised HDS SPITDS face (SPI) Port—Slave Timing ................................... 47 Revised BGA Data for Use with Surface-Mount Design ... 69 Added several new ADSP-BF516 models. Rev Page August 2010 , t parameters in Serial Peripheral Inter- SDSCI Ordering Guide 70 ...
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... PROCESSOR PERIPHERALS The ADSP-BF51x processors contain a rich set of peripherals connected to the core via several high bandwidth buses, provid ing flexibility in system configuration as well as excellent overall system performance (see contain dedicated network communication modules and high 1 – 1 – ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields. ...
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... C/C++ compiler, resulting in fast and efficient software implementations. MEMORY ARCHITECTURE The ADSP-BF51x processors view memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space ...
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... SPI flash (for signal descriptions, see Table 2 on Page 7). To further provide a secure processing envi- ronment, these internally connected signals are not exposed outside of the package. For this reason, programming the ADSP-BF51xF flash memory is performed by running code on Combinational Logic 0 Truth Table 1 ...
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... The device is enabled by a high to low transition on CE. CE must remain low for the duration of any command sequence. Resets the operation of the device and the internal logic. This signal is tied to the ADSP-BF51x RESET signal. Prioritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest priority interrupts (IVG15–14) are recommended to be reserved for Table 3. Core Event Controller (CEC) ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Table 4. Peripheral Interrupt Assignment (Continued) Peripheral Interrupt Event UART1 Status RTC DMA 0 Channel (PPI) DMA 3 Channel (SPORT0 RX) DMA 4 Channel (SPORT0 TX/RSI) DMA 5 Channel (SPORT1 RX/SPI1) DMA 6 Channel (SPORT1 TX) TWI DMA 7 Channel (SPI0) DMA8 Channel (UART0 RX) DMA9 Channel (UART0 TX) ...
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... PWM Trip Interrupt PWM Sync Interrupt PTP Status Interrupt Event Control The ADSP-BF51x processors provide a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide. • CEC interrupt latch register (ILAT)—Indicates when events have been latched ...
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... SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF. Figure 4. External Components for RTC WATCHDOG TIMER The ADSP-BF51x processors include a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the proces- sor to a known state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software ...
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... SERIAL PORTS The ADSP-BF51x processors incorporate two dual-channel syn- chronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the fol- lowing features: 2 • ...
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... CMOS camera sensor devices. REMOVABLE STORAGE INTERFACE (RSI) The RSI controller, available on the ADSP-BF514, ADSP-BF516, ADSP-BF518, and ADSP-BF518F acts as the host interface for multi-media cards (MMC), secure digital memory cards (SD Card), secure digital input/output cards (SDIO), and CE-ATA hard disk drives ...
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... J. Most of the associated pins/balls are shared by multi- ple signals. The ports function as multiplexer controls. General-Purpose I/O (GPIO) The ADSP-BF51x processors have 40 bidirectional, general- purpose I/O (GPIO) signals allocated across three separate GPIO modules—PORTFIO, PORTGIO, and PORTHIO, associ- ated with Port F, Port G, and Port H, respectively. Each ...
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... PARALLEL PERIPHERAL INTERFACE (PPI) The ADSP-BF51x processors provide a parallel peripheral inter- face (PPI) that can connect directly to parallel analog-to-digital and digital-to-analog converters, ITU-R-601/656 video encod- ers and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock signal three frame synchronization signals, and data signals ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F of clocking to each of the processor peripherals also reduces power consumption. See Table 5 for a summary of the power settings for each mode. Table 5. Power Settings Core PLL Clock Mode/State PLL Bypassed (CCLK) Full On Enabled No Enabled Enabled On Active Enabled/ Yes Enabled Enabled On ...
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... MHz. The circuit is then modified to ensure crystal operation only at the third overtone, by adding a tuned inductor circuit as shown in ation is discussed in detail in application note (EE-168) Using Third Overtone Crystals with the ADSP-218x DSP on the Analog Devices website (www.analog.com)—use site search on “EE-168.” Rev Page August 2010 ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F The CLKBUF signal is an output signal, which is a buffered ver- sion of the input clock. This signal is particularly useful in Ethernet applications to limit the number of required clock sources in the system. In this type of application, a single 25 MHz or 50 MHz crystal may be applied directly to the pro- cessor ...
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... Boot from internal SPI memory (BMODE = 0x2)—The processor uses the internal PH8 GPIO signal to load code previously loaded to the 4M bit internal SPI flash con- nected to SPI0. Only available on the ADSP-BF512F/ ADSP-BF514F/ADSP-BF516F/ADSP-BF518F. • Boot from external SPI EEPROM or flash (BMODE = 0x3)—8-bit, 16-bit, 24-bit or 32-bit address- able devices are supported ...
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... Code density enhancements, which include intermixing of 16-bit and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits. DEVELOPMENT TOOLS The ADSP-BF51x processors are supported with a complete set ® of CROSSCORE software and hardware development tools, including Analog Devices emulators and VisualDSP++® devel- opment environment ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F LOCKBOX SECURE TECHNOLOGY DISCLAIMER Analog Devices products containing Lockbox Secure Technol- ogy are warranted by Analog Devices as detailed in the Analog Devices Standard Terms and Conditions of Sale. To our knowl- edge, the Lockbox Secure Technology, when used in accordance with the data sheet and hardware reference manual specifica- tions, provides a secure method of implementing code and data safeguards ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F SIGNAL DESCRIPTIONS The processors’ signal definitions are listed in to maintain maximum function and reduce package size and signal count, some signals have dual, multiplexed functions. In cases where signal function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Table 10. Signal Descriptions Signal Name PF8/MDC/PPI D8/SPI1SEL4 PF9/MDIO/PPI D9/TMR2 PF10/ETxD0/PPI D10/TMR3 PF11/ERxD0/PPI D11/PWM AH/TACI3 PF12/ETxD1/PPI D12/PWM AL PF13/ERxD1/PPI D13/PWM BH PF14/ETxEN/PPI D14/PWM BL 2 PF15 /RMII PHYINT/PPI D15/PWM_SYNCA Port G: GPIO and Multiplexed Peripherals 3 PG0/MIICRS/RMIICRS/HWAIT /SPI1SEL3 PG1/ERxER/DMAR1/PWM CH PG2/MIITxCLK/RMIIREF_CLK/DMAR0/PWM CL I/O PG3/DR0PRI/RSI_DATA0/SPI0SEL5/TACLK3 PG4/RSCLK0/RSI_DATA1/TMR5/TACI5 ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Table 10. Signal Descriptions Signal Name Port J PJ0:SCL PJ1:SDA Real Time Clock RTXI RTXO JTAG Port TCK TDO TDI TMS TRST EMU Clock CLKIN XTAL CLKBUF Mode Controls RESET NMI BMODE2-0 Voltage Regulation Interface PG EXT_WAKE Power Supplies V DDEXT ...
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... Bidirectional pins/balls (PF15–0, PG15–0, PH7–0) and input pins/balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF51x are 3.3 V tolerant (always accept up to 3.6 V maximum V 7 Parameter value applies to all input and bidirectional pins/balls except SDA and SCL ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Table 11 shows settings for TWI_DT in the NONGPIO_DRIVE register. Set this register prior to using the TWI port. Table 11. TWI_DT Field Selections and V TWI_DT V Nominal DDEXT 000 (default) 3.3 001 1.8 010 2.5 011 1.8 100 3.3 101 1.8 110 2 ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F ELECTRICAL CHARACTERISTICS Parameter V High Level Output Voltage OH V High Level Output Voltage OH V High Level Output Voltage OH V Low Level Output Voltage High Level Input Current Low Level Input Current High Level Input Current JTAG V IHP 3 I Three-State Leakage Current ...
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... Applies to three-statable balls. 4 Applies to bidirectional balls SCL and SDA. 5 Applies to all signal balls, except SCL and SDA. 6 Guaranteed, but not tested. 7 See the ADSP-BF51x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. 8 Includes current and V DDEXT DDMEM ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Table 16. Static Current—I DD-DEEPSLEEP 1 T (°C) 1. –40 1.0 1.0 –20 1.1 1.2 0 1.3 1.4 25 1.9 2.1 40 2.6 2.8 55 3.5 3.8 70 5.0 5.4 85 7.1 7.7 100 10.0 10.8 105 11.1 12.1 1 Valid frequency and voltage ranges are model-specific. See Table 17 ...
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... When programming OTP memory on the ADSP-BF51x proces- sor, the V may cause perma- the Operating Conditions on Page of cumulative time that the write voltage may be applied (dependent on voltage and junction temperature the lifetime of the part. Therefore, maximum OTP memory pro- gramming time for the processor is shown in Table 22 ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F PACKAGE INFORMATION The information presented in Figure 7 details about the package branding for the processor. For a com- plete listing of product availability, see Ordering Guide on Page 70. ADSP-BF51x tppZccc vvvvvv.x n.n #yyww country_of_origin Figure 7. Product Information on Package Table 25. Package Brand Information ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F TIMING SPECIFICATIONS Clock and Reset Timing Table 26 and Figure 8 describe clock and reset operations. Per Absolute Maximum Ratings on Page 30, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of 400 MHz/100 MHz. Table 26. Clock and Reset Timing ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Flash Reset Timing Driving the RESET pin low resets the Flash device. Driving the RESET pin high puts the device in normal operating mode. The SO pin is in high impedance state while the device is in reset. A successful reset will reset the status register to its power-up state. ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Asynchronous Memory Read Cycle Timing Table 29. Asynchronous Memory Read Cycle Timing Parameter Timing Requirements t DATA15–0 Setup Before CLKOUT SDAT t DATA15–0 Hold After CLKOUT HDAT t ARDY Setup Before CLKOUT SARDY t ARDY Hold After CLKOUT HARDY Switching Characteristics ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Asynchronous Memory Write Cycle Timing Table 30. Asynchronous Memory Write Cycle Timing Parameter Timing Requirements t ARDY Setup Before CLKOUT SARDY t ARDY Hold After CLKOUT HARDY Switching Characteristics t DATA15–0 Disable After CLKOUT DDAT t DATA15–0 Enable After CLKOUT ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F SDRAM Interface Timing Table 31. SDRAM Interface Timing Parameter Timing Requirements t Data Setup Before CLKOUT SSDAT t Data Hold After CLKOUT HSDAT Switching Characteristics 1 t CLKOUT Period SCLK t CLKOUT Width High SCLKH t CLKOUT Width Low SCLKL t Command, Address, Data Delay After CLKOUT ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F External DMA Request Timing Table 32 and Figure 14 describe the External DMA Request operations. Table 32. External DMA Request Timing Parameter Timing PRequirements t DMARx Asserted to CLKOUT High Setup DR t CLKOUT High to DMARx Deasserted Hold Time DH t DMARx Active Pulse Width ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Parallel Peripheral Interface Timing Table 33 and Figure 15 on Page 38, Figure 21 on Page Figure 24 on Page 45 describe parallel peripheral interface operations. Table 33. Parallel Peripheral Interface Timing Parameter Timing Requirements t PPI_CLK Width PCLKW t PPI_CLK Period PCLK Timing Requirements - GP Input and Frame Capture Modes ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F FRAME SYNC DATA DRIVEN SAMPLED PPI_CLK t DFSPE t HOFSPE PPI_FS1/2 t SDRPE PPI_DATA Figure 17. PPI GP Rx Mode with Internal Frame Sync Timing FRAME SYNC DRIVEN PPI_CLK t DFSPE t HOFSPE PPI_FS1/2 PPI_DATA Figure 18. PPI GP Tx Mode with Internal Frame Sync Timing ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F RSI Controller Timing Table 34 and Figure 19 describe RSI controller timing. and Figure 20 describe RSI controller (high speed) timing. Table 34. RSI Controller Timing Parameter Timing Requirements t Input Setup Time ISU t Input Hold Time IH Switching Characteristics 1 f Clock Frequency Data Transfer Mode ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Table 35. RSI Controller Timing (High Speed Mode) Parameter Timing Requirements t Input Setup Time ISU t Input Hold Time IH Switching Characteristics 1 f Clock Frequency Data Transfer Mode PP t Clock Low Time WL Clock High Time Clock Rise Time TLH t Clock Fall Time ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Serial Ports Table 36 through Table 39 on Page 45 and through Figure 24 on Page 45 describe serial port operations. Table 36. Serial Ports—External Clock Parameter Timing Requirements t TFSx/RFSx Setup Before TSCLKx/RSCLKx SFSE t TFSx/RFSx Hold After TSCLKx/RSCLKx HFSE t Receive Data Setup Before RSCLKx ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F t SCLKIW RSCLKx t DFSI t HOFSI RFSx (OUTPUT) t SFSI RFSx (INPUT) t SDRI DRx DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKIW TSCLKx t D FSI t HOFSI TFSx (OUTPUT) t SFSI TFSx (INPUT) t DDTI t HDTI DTx TSCLKx (INPUT) TFSx (INPUT) RSCLKx ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Table 38. Serial Ports—Enable and Three-State Parameter Switching Characteristics t Data Enable Delay from External TSCLKx DTENE t Data Disable Delay from External TSCLKx DDTTE t Data Enable Delay from Internal TSCLKx DTENI t Data Disable Delay from Internal TSCLKx DDTTI 1 Referenced to drive edge ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Table 39. External Late Frame Sync Parameter Switching Characteristics t Data Delay from Late External TFSx or External RFSx with DDTLFSE 1, 2 MCE = 1, MFD = 0 t Data Enable from Late FS or MCE = 1, MFD = 0 DTENLFSE 1 MCE = 1, TFSx enable and TFSx valid follow t ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Serial Peripheral Interface (SPI) Port—Master Timing Table 40 and Figure 25 describe SPI port master operations. Table 40. Serial Peripheral Interface (SPI) Port—Master Timing Parameter Timing Requirements t Data Input Valid to SCK Edge (Data Input Setup) SSPIDM t SCK Sampling Edge to Data Input Invalid ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Serial Peripheral Interface (SPI) Port—Slave Timing Table 41 and Figure 26 describe SPI port slave operations. Table 41. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Timing Requirements t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t Serial Clock Period ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing The UART ports receive and transmit operations are described in the ADSP-BF51x Hardware Reference Manual. General-Purpose Port Timing Table 42 and Figure 27 describe general-purpose port operations. Table 42. General-Purpose Port Timing ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Timer Cycle Timing Table 44 and Figure 29 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external clock mode” and has an absolute maximum input fre- quency of (f /2) MHz. SCLK Table 44. Timer Cycle Timing ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Up/Down Counter/Rotary Encoder Timing Table 45. Up/Down Counter/Rotary Encoder Timing Parameter Timing Requirements t Up/Down Counter/Rotary Encoder Input Pulse Width WCOUNT t Counter Input Setup Time Before CLKOUT Low CIS t Counter Input Hold Time After CLKOUT Low CIH 1 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs. ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F 10/100 Ethernet MAC Controller Timing Table 46 through Table 51 and Figure 31 describe the 10/100 Ethernet MAC Controller operations. Table 46. 10/100 Ethernet MAC Controller Timing: MII Receive Signal 1 Parameter Timing Requirements t ERxCLK Frequency (f = SCLK Frequency) ERXCLKF SCLK t ERxCLK Width (t ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Table 48. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal 1 Parameter Timing Requirements t REF_CLK Frequency (f = SCLK Frequency) EREFCLKF SCLK t EREF_CLK Width (t = EREFCLK Period) EREFCLKW EREFCLK t Rx Input Valid to RMII REF_CLK Rising Edge (Data In EREFCLKIS Setup) t RMII REF_CLK Rising Edge to Rx Input Invalid (Data In ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Table 50. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal Parameter Timing Requirements 1 t COL Pulse Width High ECOLH 1 t COL Pulse Width Low ECOLL 2 t CRS Pulse Width High ECRSH 2 t CRS Pulse Width Low ECRSL 1 MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1 ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F JTAG Test And Emulation Port Timing Table 52 and Figure 37 describe JTAG port operations. Table 52. JTAG Port Timing Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F OUTPUT DRIVE CURRENTS Figure 38 through Figure 52 show typical current-voltage char- acteristics for the output drivers of the ADSP-BF51xF processors. 200 160 120 –40 –80 –120 –160 –200 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 38. Driver Type A Current (3.3V V ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F 100 –20 –40 –60 –80 –100 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 44. Driver Type C Current (3. –20 –40 –60 –80 0 0.5 1.0 1.5 SOURCE VOLTAGE (V) Figure 45. Drive Type C Current (2. –10 –20 –30 –40 0 0.5 1.0 SOURCE VOLTAGE (V) Figure 46 ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F –10 –20 –30 –40 –50 –60 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V) Figure 50. Driver Type E Current (3.3V V DDEXT –10 –20 –30 –40 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V) Figure 51. Driver Type E Current (2.5V V DDEXT 20 15 ...
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... To determine the data output hold time in a particular system, using the equation given above. Choose ΔV first calculate t DECAY to be the difference between the ADSP-BF51x processor’s out- put voltage and the input threshold for the device requiring the hold time the total bus capacitance (per data line), and I L the total leakage or three-state current (per data line) ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F RISE 100 150 LOAD CAPACITANCE (pF) Figure 57. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2. DDEXT DDMEM RISE 100 150 LOAD CAPACITANCE (pF) Figure 58. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (3. DDEXT DDMEM 100 ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F 100 LOAD CAPACITANCE (pF) Figure 63. Driver Type C Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2.5V V DDEXT 100 LOAD CAPACITANCE (pF) Figure 64. Driver Type C Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (3.3V V DDEXT 100 LOAD CAPACITANCE (pF) Figure 65. Driver Type D Typical Rise and Fall Times (10%–90%) vs. ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F THERMAL CHARACTERISTICS To determine the junction temperature on the application printed circuit board use: ( Ψ CASE JT where Junction temperature ( ° Case temperature ( C) measured by customer at top ° CASE center of package. Ψ = From Table Power dissipation (see Total Power Dissipation on Page 28 ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F 176-LEAD LQFP LEAD ASSIGNMENT Table 55 lists the LQFP leads by lead number. Table 55. 176-Lead LQFP Pin Assignment (Numerically by Lead Number) Lead No. Signal Lead No. 1 GND 45 2 GND 46 3 PF9 47 4 PF8 48 5 PF7 49 6 PF6 DDEXT PPOTP DDOTP ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Table 56. 176-Lead LQFP Pin Assignment (Alphabetically by Signal Mnemonic) Lead No. Signal Lead No. 107 A1 58 106 A2 57 105 A3 56 103 A4 51 102 A5 130 101 A10 43 92 A11 44 91 A12 45 86 A13 46 85 A14 67 84 A15 83 81 A16 87 80 A17 ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Figure 68 shows the top view of the LQFP_EP lead configura- tion. Figure 69 shows the bottom view of the LQFP_EP lead configuration. PIN 1 INDICATOR ADSP-BF51X 176-LEAD LQFP_EP BOTTOM VIEW PIN 176 PIN 133 PIN 1 ADSP-BF51X 176-LEAD LQFP_EP TOP VIEW PIN 44 ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F 168-BALL CSP_BGA BALL ASSIGNMENT Table 57 lists the CSP_BGA by ball number. Page 66 lists the CSP_BGA balls by signal mnemonic. Table 57. 168-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Table 58. 168-Ball CSP_BGA Ball Assignment (Alphabetically by Signal Mnemonic) Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name K14 A1 A11 CLKBUF K13 A2 A13 CLKIN H12 A3 D13 CLKOUT L14 A4 M9 ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Figure 70 shows the top view of the CSP_BGA ball configura- tion. Figure 71 shows the bottom view of the CSP_BGA ball configuration. A1 BALL PAD CORNER TOP VIEW Figure 70. 168-Ball CSP_BGA Ball Configuration (Top View BOTTOM VIEW Figure 71. 168-Ball CSP_BGA Ball Configuration (Bottom View) Rev ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F OUTLINE DIMENSIONS Dimensions in Figure 72 are shown in millimeters. 0.75 0.60 0.45 1.00 REF 12° 1.45 0.20 1.40 0.15 1.35 0.09 7° 0.15 0° 0.10 SEATING 0.08 MAX PLANE 0.05 COPLANARITY VIEW A ROTATED 90 ° CCW 26.20 26.00 SQ 25.80 24.10 24 ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F A1 BALL CORNER 1.70 1.60 1.45 SURFACE-MOUNT DESIGN Table 59 is provided as an aid to PCB design. For industry standard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 59. BGA Data for Use with Surface-Mount Design ...
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... ADSP-BF512KSWZ-4 0ºC to +70ºC ADSP-BF512KSWZ-4F4 0ºC to +70ºC ADSP-BF514BBCZ-3 –40ºC to +85ºC ADSP-BF514BBCZ-4 –40ºC to +85ºC ADSP-BF514BBCZ-4F4 –40ºC to +85ºC ADSP-BF514BSWZ-3 –40ºC to +85ºC ADSP-BF514BSWZ-4 –40ºC to +85ºC ADSP-BF514BSWZ-4F4 –40ºC to +85ºC ADSP-BF514KBCZ-3 0º ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Temperature 1 2 Model Range ADSP-BF514KSWZ-4F4 0ºC to +70ºC ADSP-BF516KSWZ-3 0ºC to +70ºC ADSP-BF516KBCZ-3 0ºC to +70ºC ADSP-BF516KSWZ-4 0ºC to +70ºC ADSP-BF516KBCZ-4 0ºC to +70ºC ADSP-BF516KSWZ-4F4 0ºC to +70ºC ADSP-BF516KBCZ-4F4 0ºC to +70ºC ADSP-BF516BBCZ-3 –40ºC to +85ºC ADSP-BF516BBCZ-4 – ...
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... ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08574-0-8/10(A) Rev Page August 2010 ...