ADP2504-EVALZ Analog Devices Inc, ADP2504-EVALZ Datasheet - Page 11

• Manufacturer Part Number: ADP2504-EVALZ
• Description: 1A Buck/Boost DC/DC Converter
• Manufacturer: Analog Devices Inc

Specifications of ADP2504-EVALZ

• Main Purpose: DC/DC, Step Up or Down
• Current - Output: 1A
• Voltage - Input: 2.5 ~ 5.5 V
• Regulator Topology: Buck-Boost
• Frequency - Switching: 2.5MHz
• Board Type: Fully Populated
• Utilized Ic / Part: ADP2504
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Power - Output: -
• Outputs And Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
The ADP2503/ADP2504 are synchronous average current-
mode switching buck-boost regulators designed to maintain a
fixed output voltage V
greater than, equal to, or less than V
cantly greater than V
always active, NMOS2 is always off, and the PMOS1 and NMOS1
switches constitute a buck converter. When V
lower than V
active, NMOS1 is always off, and the NMOS2 and PMOS2
switches constitute a boost converter. When V
[V
buck-boost mode. In buck-boost mode, the two operations,
buck (PMOS1 and NMOS1 switching in antiphase) and boost
(NMOS2 and PMOS2 switching in antiphase), take place at each
period of the clock. This is aimed at maintaining the regulation
and keeping a minimal current ripple in the inductor to guaran-
tee good transient performances.
POWER SAVE MODE
When the SYNC pin is low, the ADP2503/ADP2504 can operate
in power save mode (PSM). In this mode, when the load current
becomes less than 75 mA nominally at V
ler pulls up V
goes back to a restart value. Then V
new cycle. This minimizes the switching losses at light load. When
the load rises above 150 mA, the ADP2503/ADP2504 revert to
fixed PWM mode. This results in about 75 mA of hysteresis
OUT
± 10%], the ADP2503/ADP2504 automatically enter the
OUT
OUT
, the device is in boost mode: PMOS1 is always
VBAT = 2.3V
and then halts the switching regime until V
TO 5.5V
OUT
10µF
OUT
, the device is in buck mode: PMOS2 is
from an input supply V
EN
8
5
6
7
VIN
PVIN
EN
SYNC
REFERENCE
BAND GAP
OUT
OUT
PGND
2.25V
. When V
ADP2503/ADP2504
is pulled up again for a
UVLO
IN
3
= 3.6 V, the control-
BIASING
IN
IN
is significantly
is in the range
PROTECTION
IN
IN
PMOS1
THERMAL
Figure 29. ADP2503/ADP2504 Block Diagram
9
is signifi-
that can be
AGND
NMOS1
SW1
Rev. A | Page 11 of 16
OSCILLATOR
OUT
4
PWM CONTROL
1.5µH
NMOS2
between PSM and fixed PWM, preventing oscillations between
these two modes.
SOFT START
When the ADP2503/ADP2504 are started, V
0 V to its final programmed value in 200 μs (typical). This limits
the inrush current to less than 600 mA for a nominal output
capacitor of 20 μF. Because the V
the inrush current becomes larger if the output capacitor is
made larger.
SYNC FUNCTION
When the SYNC pin is high, PSM is deactivated. The ADP2503/
ADP2504 always operate in PWM using the internal oscillator.
When the SYNC pin is switching in the 2.1 MHz to 2.9 MHz
range,
quency applied on SYNC and then locks on it. When the
SYNC pin stops switching, the regulator switching frequency
slides back to the internal oscillator frequency.
ENABLE
The device starts operation with soft start when the EN pin
is brought high. Pulling the EN pin low forces the device into
shutdown, with a typical shutdown current of 0.2 μA.
In this mode, the PMOS power switches are turned off, the
NMOS power switches are turned on, and the control circuitry
is not enabled. For proper operation, the EN pin must be
terminated and must not be left floating.
2
SW2
the regulator switching frequency slides to the fre-
ADP2503/ADP2504
CS
PMOS2
SOFT START
–0.5V
VOUT
FB
OUT
10
ADP2503/ADP2504
1
start-up slope is constant,
22µF
OUT
is ramped from