AD9522-5/PCBZ Analog Devices Inc, AD9522-5/PCBZ Datasheet - Page 71

• Manufacturer Part Number: AD9522-5/PCBZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc

Specifications of AD9522-5/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9522-5
• Primary Attributes: 12 LVDS/24 CMOS Outputs
• Secondary Attributes: I²C & SPI Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
19B
19B
Reg.
Addr
(Hex) Bit(s) Name
1E0
1E1
1E1
Table 50. VCO Divider and CLK Input
Table 51. System
Reg.
Addr
(Hex) Bit(s) Name
230
230
230
230
[2:0]
[4]
[0]
[3]
[2]
[1]
[0]
[2]
[0]
VCO divider
Power-down clock input section Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
Bypass VCO divider
Disable power-on SYNC
Power-down SYNC
Power-down distribution reference
Soft SYNC
Channel 3 power-down
Disable Divider 3 DCC
Description
Channel 3 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT9/OUT9, OUT10/OUT10, and OUT11/OUT11 are put into the high
impedance power-down mode by setting this bit.)
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
Description
[2]
0
0
0
0
1
1
1
1
[4] = 0; normal operation (default).
[4] = 1; power down.
Bypasses or uses the VCO divider.
[0] = 0; use VCO divider (default).
[0] = 1; bypass VCO divider.
Description
Power-on SYNC mode. Used to disable the antiruntpulse circuitry.
[3] = 0; enable the antiruntpulse circuitry (default).
[3] = 1; disable the antiruntpulse circuitry.
Powers down the SYNC function.
[2] = 0; normal operation of the SYNC function (default).
[2] = 1; power-down the SYNC circuitry.
Powers down the reference for the distribution section.
[1] = 0; normal operation of the reference for the distribution section (default).
[1] = 1; powers down the reference for the distribution section.
The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit
is reversed; that is, a high level forces the selected channels into a predetermined
static state, and a 1-to-0 transition triggers a SYNC.
[0] = 0; same as SYNC high.
[0] = 1; same as SYNC low.
Rev. 0 | Page 71 of 76
[1]
0
0
1
1
0
0
1
1
[0]
0
1
0
1
0
1
0
1
Divide
2 (default)
3
4
5
6
Output static
1 (bypass)
Output static
AD9522-5