AD9516-1BCPZ Analog Devices Inc, AD9516-1BCPZ Datasheet - Page 41

• Manufacturer Part Number: AD9516-1BCPZ
• Description: IC,Fourteen Distributed-Output Clock Driver,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-1BCPZ

• Pll: Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.65GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.65GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9516-1/PCBZ - BOARD EVALUATION FOR AD9516-1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To connect the LVPECL outputs directly to the internal VCO or
CLK, the VCO divider must be selected as the source to the
distribution section, even if no channel uses it.
Either the internal VCO or the CLK can be selected as the
source for the direct to output routing.
Table 31. Settings for Routing VCO Divider Input Directly
to LVPECL Outputs
Register Setting
0x1E1[1:0] = 00b
0x1E1[1:0] = 10b
0x192[1] = 1b
0x195[1] = 1b
0x198[1] = 1b
Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the VCO or CLK to the
output is the product of the VCO divider (2, 3, 4, 5, 6) and the
division of the channel divider. Table 32 and Table 33 indicate
how the frequency division for a channel is set. For the LVPECL
outputs, there is only one divider per channel. For the LVDS/
CMOS outputs, there are two dividers (X.1, X.2) cascaded
per channel.
Table 32. Frequency Division for Divider 0 to Divider 2
CLK
or VCO
Selected
CLK/VCO
CLK/VCO
CLK/VCO
CLK
CLK
Table 33. Frequency Division for Divider 3 and Divider 4
CLK
or VCO
Selected
CLK/VCO
CLK/VCO
CLK/VCO
CLK
CLK
CLK
VCO
Divider
2 to 6
2 to 6
2 to 6
Not used
Not used
VCO
Divider
2 to 6
2 to 6
2 to 6
Not used
Not used
Not used
Selection
CLK is the source; VCO divider selected
VCO is the source; VCO divider selected
Direct to output OUT0, OUT1
Direct to output OUT2, OUT3
Direct to output OUT4, OUT5
X.1
1
(bypassed)
1
2 to 32
2 to 32
Channel
Divider
1 (bypassed)
1 (bypassed)
2 to 32
1 (bypassed)
2 to 32
2 to 32
2 to 32
Channel Divider
X.2
1
(bypassed)
1
(bypassed)
2 to 32
1
1
2 to 32
Direct to
Output
Yes
No
No
No
No
Frequency
Division
1
(2 to 6) × (1)
(2 to 6) ×
(2 to 32)
1
2 to 32
Frequency
Division
(2 to 6) ×
(1) × (1)
(2 to 6) ×
(2 to 32) × (1)
(2 to 6) ×
(2 to 32) ×
(2 to 32)
1
(2 to 32) × (1)
2 to 32 ×
(2 to 32)
Rev. A | Page 41 of 80
The channel dividers feeding the LVPECL output drivers
contain one 2-to-32 frequency divider. This divider provides for
division by 2 to 32. Division by 1 is accomplished by bypassing
the divider. The dividers also provide for a programmable duty
cycle, with optional duty-cycle correction when the divide ratio
is odd. A phase offset or delay in increments of the input clock
cycle is selectable. The channel dividers operate with a signal at
their inputs up to 1600 MHz. The features and settings of the
dividers are selected by programming the appropriate setup
and control registers (see Table 52 through Table 62).
VCO Divider
The VCO divider provides frequency division between the
internal VCO or the external CLK input and the clock
distribution channel dividers. The VCO divider can be set
to divide by 2, 3, 4, 5, or 6 (see Table 60, Register 0x1E0[2:0]).
Channel Dividers—LVPECL Outputs
Each pair of LVPECL outputs is driven by a channel divider.
There are three channel dividers (0, 1, and 2) driving a total of
six LVPECL outputs (OUT0 to OUT5). Table 34 lists the register
locations used for setting the division and other functions of
these dividers. The division is set by the values of M and N. The
divider can be bypassed (equivalent to divide-by-1, divider circuit
is powered down) by setting the bypass bit. The duty-cycle
correction can be enabled or disabled according to the setting of
the DCCOFF bits.
Table 34. Setting D
Divider
0
1
2
1
Channel Frequency Division (0, 1, and 2)
For each channel (where the channel number is x: 0, 1, or 2),
the frequency division, D
(four bits each, representing Decimal 0 to Decimal 15), where
The cycles are cycles of the clock signal currently routed to the
input of the channel dividers (VCO divider out or CLK).
When a divider is bypassed, D
Otherwise, D
each channel divider to divide by any integer from 2 to 32.
Note that the value stored in the register = # of cycles minus 1.
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
Low Cycles
M
0x190[7:4]
0x193[7:4]
0x196[7:4]
X
= (N + 1) + (M + 1) = N + M + 2. This allows
X
for Divider 0, Divider 1, and Divider 2
X
High Cycles
N
0x190[3:0]
0x193[3:0]
0x196[3:0]
, is set by the values of M and N
X
= 1.
Bypass
0x191[7]
0x194[7]
0x197[7]
AD9516-1
DCCOFF
0x192[0]
0x195[0]
0x198[0]
1