DSDK2000 Maxim Integrated Products, DSDK2000 Datasheet - Page 12

• Manufacturer Part Number: DSDK2000
• Description: Power Management Modules & Development Tools HIGH PERFORMANCE DEM CE DEMO KIT PLATFORM
• Manufacturer: Maxim Integrated Products

Specifications of DSDK2000

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPENDIX
MPC8260 CPU and Memory Map
CPU Core. The DK2000 development platform is based on the Motorola MPC8260 PowerQUICC II processor. This
processor integrates a PowerPC core, a system interface unit (SIU), and a communications processor module
(CPM).
The DK2000 board is configured with a 66MHz oscillator providing the system bus clock and SIU clocks. The
MPC8260 internally multiplies the system clock to 133MHz for the CPM and to 200MHz for the PowerPC processor
core. The internal clock multiplier is determined during PORESET (power-on RESET) based on the states of
RSTCONF, MODCLK [1–3], and the values in the hard-reset configuration word bits 28–31. The DK2000 board
wires RSTCONF low, forcing the MPC8260 to read the hard-reset configuration word from the beginning of flash
memory. DK2000 ’s default configuration word is configurable depending on your application. Refer to the Motorola
MPC8260 PowerQUICC II User’s Manual, Section 5.4.1 (www.motorola.com) for detailed information about reset
configuration.
SDRAM. The DK2000 development platform contains 64MB of SDRAM controlled by the MPC8260’s internal
SDRAM controller. The SDRAM is connected to the MPC8260’s chip select 2 (CS2).
Level 2 Cache Control. To provide additional performance, the DK2000 board has been designed with the option
for 256kB, 512kB, or 1MB of L2 cache. One, two, or four MPC2605s are used as the L2 cache. The MPC2605 can
function in either copy-back mode or write-through mode. The L2 cache can be enabled and disabled though a
register in the EPLD at CS11 + 0x01. This register controls four signals: L2_FLUSH_L, L2_MISS_INH_L,
L2_TAG_CLR_L, AND L2_UPDATE_INH_L. The board powers up with the L2 cache disabled; software must
configure the MPC8260 to work with the L2 cache before enabling it. See
control register.
FLASH—2 Banks. The DK2000 development platform has 4MB of flash memory organized into two banks. Each
bank is organized as 512kB x 32, consisting of four Atmel AT49LV040 devices that are socketed for easy removal
and external programming. Through jumper selection, either of the two flash banks can be configured as the boot
ROM. The flash banks are controlled by the MPC8260’s chip selects 0 and 1 (CS0 and CS1). The chip-select
assignment for each bank is a jumper-configurable selection. The silk screening on the board next to the BOOT
CONFIG header (P7) indicates which byte lane each FLASH device is attached to. See
EEPROM. A 16kb EEPROM is connected to the SPIÔ port on the MPC8260. The EEPROM is organized as 2048
x 8.
Chip-Select Mapping
The MPC8260 has 12 chip-select outputs. The DK2000 board uses these chip selects as defined in
CS0 and CS1. Chip selects 0 and 1 are connected to the two 2MB flash banks through jumper block P7. To
connect CS0 to bank 0 and CS1 to bank 1, place a jumper across pins 1 and 2 and another jumper across pins 3
and 4. To connect CS0 to bank 1 and CS1 to bank 0, place a jumper across pins 1 and 3 and another jumper
across pins 2 and 4. See
CS7. Chip select 7 addresses the STIM board ID and LED control register as shown in
SPI is a trademark of Motorola, Inc.
RESET CONFIGURATION BYTE
Figure
5.
0
1
2
3
12 of 19
DEFAULT DK2000 VALUE
0x1E
0x82
0x83
0x45
Table 7
for a description of the L2 cache
Table
Figure
5.
4.
Table
4.