TLE8209-2SA Infineon Technologies, TLE8209-2SA Datasheet - Page 25

• Manufacturer Part Number: TLE8209-2SA
• Description: IC H-BRIDGE SPI PROG DSO-20
• Manufacturer: Infineon Technologies

Specifications of TLE8209-2SA

• Applications: DC Motor Driver
• Number Of Outputs: 1
• Voltage - Load: 4.5 V ~ 28 V
• Voltage - Supply: 4.4 V ~ 5.25 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (0.433", 11.0mm Width) Exposed Pad
• Packages: PG-DSO-20
• Current Limit (min.): 7.7 A
• Rthjc (max): 1.6 K/W
• Quiescent Current (max.): 20 µA
• Operating Range: 4.5 - 28 V
• Rds (on) (typ./switch): 125.0 mOhm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -

5. Verification byte: Simultaneously to the receipt of an SPI instruction the TLE8209-2SA transmits a verification
6. On a read access the data bits at the SPI input SI are rejected. During a valid write access the SPI will transmit
7. An instruction is invalid if one of the following conditions is fulfilled:
9.2
The 16 input bits consist of the SPI instruction byte and an input data byte. The 16 output bits consist of the
verification byte and the output data byte (see also
subsequent sections. The access mode of the registers is described in the column “Type” (r = read, w = write).
Figure 15
9.2.1
The upper 2 bit of the instruction byte contain the chip address. The chip address of the TLE8209-2SA is ’00’.
During read access, the output data according to the register requested in the instruction byte are applied to SO
within the same SPI frame. That means, the output data corresponding to an instruction byte sent during one SPI
frame are transmitted to SO during the same SPI-frame
Data Sheet
address). If the chip address does not match, the according frame will be ignored and SO remains tristate for
the complete frame.
byte via the output SO to the controller. This byte indicates regular or irregular operation of the SPI. It contains
an initial bit pattern and a flag indicating an invalid instruction of the previous access.
the data byte "00hex" at the output SO after having sent the verification byte.
- an unused instruction code is detected (see tables with SPI instructions).
- the previous transmission is not completed in terms of internal data processing.
- the number of SPI clock pulses (falling edge) counted during active SS differs from exactly 16 clock pulses.
If an unused instruction code occurres, the data byte “FF
verification byte. This transmission takes place within the same SPI-frame that contained the unused
instruction byte.
If an invalid instruction is detected, bit TRANS_F in the following verification byte (next SPI-transmission) is set
to HIGH. The TRANS_F bit must not be cleared before it has been sent to the microcontroller.
SCK
SO
SS
SI
SPI Communication
SPI Communication
Instruction Byte
MSB
MSB
7
6
5
Verification byte
SPI Instruction
4
3
2
1
Figure
LSB
LSB MSB
0
25
hex
7
” (no error) will be transmitted after having sent the
15). The definition of these bytes is given in the
6
5
output data-byte
input data-byte
4
3
2
1
Rev. 1.0, 2010-02-16
0
LSB
TLE8209-2SA
SPI Interface