LTM-8328PKR-04 Lite-On Electronics, LTM-8328PKR-04 Datasheet - Page 5

• Manufacturer Part Number: LTM-8328PKR-04
• Description: LED Displays Red 638nm 155ucd 4-Digit
• Manufacturer: Lite-On Electronics
• Type: Panelr

Specifications of LTM-8328PKR-04

• Illumination Color: Bright Red
• Package Type: DIP
• Number Of Digits: 4
• Product Length (mm): 40.4mm
• Product Height (mm): 5.1mm
• Product Depth (mm): 20.4mm
• Digit Size (in): .3in
• Character Displayed: Numeric
• Viewing Area Length (mm): 4.76mm
• Viewing Area Height (mm): 7.62mm
• Emitting Color: B. Red
• Forward Voltage: 3.5V
• Test Current (it): 20mA
• Forward Current: 8.5mA
• Dominant Wave Length: 638nm
• Power Dissipation: 335mW
• Luminous Intensity: 155ucd
• Total Thickness: 3.5mm
• Operating Supply Voltage (typ): 5/9V
• Mounting: Through Hole
• Operating Temperature Classification: Commercial
• Pin Count: 9
• Number Of Elements: 32
• Operating Supply Voltage (max): 11V
• Operating Supply Voltage (min): 4.75V
• Peak Wavelength: 697nm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

   

   
 
ELECTRICAL OPTICAL CHARACTERISTICS AT T
signals serial data and clock. Using a format of a leading “1” following by the 35 data bits
allows data transfer without an additional load signal. The 35 data bits are latched after the
36
change only if the serial data bits differ from the previous time.
capacitor should be connected to brightness control, Pin 7 to prevent possible oscillations.
The output current is typically 25 times greater than the current into Pin 7 which is set by an
external variable resistor. There is an internal limiting resistor of 400
Figure 1 shows the input data format. A start bit of logical “1” proceed the 35 bits of data. At
the 36
which loads the 35 bits of the shift registers into the latches. At the low state of the clock a
RESET signal is generated which clears all the shift registers for the next set of data. The
shift registers are static master-slave configuration. There is no clear for portion of the first
register, thus allowing continuous operation.
is first applied to the chip an internal power ON reset signal is generated which reset all
registers and all latched. The ATART bit and first clock return the chip on its normal
operation. Bit 1 is the first following the start bit and it will appear on the Figure 2 shows the
timing relationship between data clock, and DATA ENABLE. A maximum clock frequency of
0.5 MHz is assumed.
Average Luminous Intensity
Peak Emission Wavelength
Spectral Line Half-Width
Dominant Wavelength
Luminous Intensity Matching Ratio
FUNCTIONAL DESCRIPTION
th
Serial data transfer from the data source to the display driver is accomplished with 2
Brightness of display is determined by control the 0utput current of LED display. A 1nF
There must be a complete set of 36 clocks or the shift registers won’t clear. When power
bit is completed, thus providing non-multiplexed, direct drive to the display. Outputs
th
clock, a LOAD signal is generated synchronously with the high state of the clock,
PARAMETER



  


       
SYMBOL MIN. TYP. MAX. UNIT
!
Iv-m
Iv
p
d
79
155
697
638
90
A
2:1
=

  
25
o
C
ucd
nm
nm
nm
nominal value.
TEST CONDITION
I
I
I
I
I
B
B
B
B
F
=0.4mA
=0.4mA
=0.4mA
=0.4mA
=20mA