PN5120A0HN1/C2,151 NXP Semiconductors, PN5120A0HN1/C2,151 Datasheet - Page 121

• Manufacturer Part Number: PN5120A0HN1/C2,151
• Description: IC TRANSMISSION MOD 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN1/C2,151

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 78. PageReg register (address 20h); reset value: 00h,
Table 79. Description of PageReg bits . . . . . . . . . . . . . . .48
Table 80. CRCResultReg register (address 21h); reset
Table 81. Description of CRCResultReg bits . . . . . . . . . .48
Table 82. CRCResultReg register (address 22h); reset
Table 83. Description of CRCResultReg bits . . . . . . . . . .48
Table 84. GsNOffReg register (address 23h); reset value:
Table 85. Description of GsNOffReg bits . . . . . . . . . . . . .49
Table 86. ModWidthReg register (address 24h); reset value:
Table 87. Description of ModWidthReg bits . . . . . . . . . . .50
Table 88. TxBitPhaseReg register (address 25h); reset
Table 89. Description of TxBitPhaseReg bits . . . . . . . . . .50
Table 90. RFCfgReg register (address 26h); reset value:
Table 91. Description of RFCfgReg bits . . . . . . . . . . . . .51
Table 92. GsNOnReg register (address 27h); reset value:
Table 93. Description of GsNOnReg bits . . . . . . . . . . . . .52
Table 94. CWGsPReg register (address 28h); reset value:
Table 95. Description of CWGsPReg bits. . . . . . . . . . . . .52
Table 96. ModGsPReg register (address 29h); reset value:
Table 97. Description of ModGsPReg bits . . . . . . . . . . . .53
Table 98. TModeReg register (address 2Ah); reset value:
Table 99. Description of TModeReg bits . . . . . . . . . . . . .53
Table 100. TPrescalerReg register (address 2Bh); reset
Table 101. Description of TPrescalerReg bits . . . . . . . . . .54
Table 102. TReloadReg (Higher bits) register (address 2Ch);
Table 103. Description of the higher TReloadReg bits . . .55
Table 104. TReloadReg (Lower bits) register (address 2Dh);
Table 105. Description of lower TReloadReg bits . . . . . . .55
Table 106. TCounterValReg (Higher bits) register (address
Table 107. Description of the higher TCounterValReg bits 56
Table 108. TCounterValReg (Lower bits) register (address
Table 109. Description of lower TCounterValReg bits . . . .56
Table 110. PageReg register (address 30h); reset value:
Table 111. Description of PageReg bits . . . . . . . . . . . . . . .57
Table 112. TestSel1Reg register (address 31h); reset value:
Table 113. Description of TestSel1Reg bits . . . . . . . . . . . .58
Table 114. TestSel2Reg register (address 32h); reset value:
Table 115. Description of TestSel2Reg bits . . . . . . . . . . . .58
Table 116. TestPinEnReg register (address 33h); reset
PN512
Product data sheet
COMPANY PUBLIC
00000000b . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
value: FFh, 11111111b. . . . . . . . . . . . . . . . . . . .48
value: FFh, 11111111b. . . . . . . . . . . . . . . . . . . .48
88h, 10001000b . . . . . . . . . . . . . . . . . . . . . . . .49
26h, 00100110b . . . . . . . . . . . . . . . . . . . . . . . .50
value: 87h, 10000111b . . . . . . . . . . . . . . . . . . .50
48h, 01001000b . . . . . . . . . . . . . . . . . . . . . . . .51
88h, 10001000b . . . . . . . . . . . . . . . . . . . . . . . .52
20h, 00100000b . . . . . . . . . . . . . . . . . . . . . . . .52
20h, 00100000b . . . . . . . . . . . . . . . . . . . . . . . .53
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .53
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .54
reset value: 00h, 00000000b . . . . . . . . . . . . . .55
reset value: 00h, 00000000b . . . . . . . . . . . . . .55
2Eh); reset value: XXh, XXXXXXXXb . . . . . . .56
2Fh); reset value: XXh, XXXXXXXXb. . . . . . . .56
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .56
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .58
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .58
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 10 March 2011
111336
Table 117. Description of TestPinEnReg bits . . . . . . . . . . 59
Table 118. TestPinValueReg register (address 34h); reset
Table 119. Description of TestPinValueReg bits . . . . . . . . 59
Table 120. TestBusReg register (address 35h); reset value:
Table 121. Description of TestBusReg bits . . . . . . . . . . . . 60
Table 122. AutoTestReg register (address 36h); reset value:
Table 123. Description of bits . . . . . . . . . . . . . . . . . . . . . . 60
Table 124. VersionReg register (address 37h); reset value:
Table 125. Description of VersionReg bits . . . . . . . . . . . . 61
Table 126. AnalogTestReg register (address 38h); reset
Table 127. Description of AnalogTestReg bits . . . . . . . . . 62
Table 128. TestDAC1Reg register (address 39h); reset
Table 129. Description of TestDAC1Reg bits . . . . . . . . . . 63
Table 130. TestDAC2Reg register (address 3Ah); reset
Table 131. Description ofTestDAC2Reg bits . . . . . . . . . . . 63
Table 132. TestADCReg register (address 3Bh); reset value:
Table 133. Description of TestADCReg bits . . . . . . . . . . . 63
Table 134. RFTReg register (address 3Ch); reset value:
Table 135. Description of RFTReg bits . . . . . . . . . . . . . . . 64
Table 136. RFTReg register (address 3Dh, 3Fh); reset value:
Table 137. Description of RFTReg bits . . . . . . . . . . . . . . . 64
Table 138. RFTReg register (address 3Eh); reset value:
Table 139. Description of RFTReg bits . . . . . . . . . . . . . . . 64
Table 140. Connection protocol for detecting different
Table 141. Connection scheme for detecting the different
Table 142. MOSI and MISO byte order . . . . . . . . . . . . . . 66
Table 143. MOSI and MISO byte order . . . . . . . . . . . . . . 67
Table 144. Address byte 0 register; address MOSI . . . . . 67
Table 145. BR_T0 and BR_T1 settings . . . . . . . . . . . . . . 68
Table 146. Selectable UART transfer speeds . . . . . . . . . 68
Table 147. UART framing . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 148. Read data byte order . . . . . . . . . . . . . . . . . . . 69
Table 149. Write data byte order . . . . . . . . . . . . . . . . . . . 69
Table 150. Address byte 0 register; address MOSI . . . . . 71
Table 151. Supported interface types . . . . . . . . . . . . . . . . 79
Table 152. Register and bit settings controlling the signal on
Table 153. Register and bit settings controlling the signal on
Table 154. Setting of the bits RFlevel in register RFCfgReg
Table 155. CRC coprocessor parameters . . . . . . . . . . . . 90
Table 156. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . 92
Table 157. Command overview . . . . . . . . . . . . . . . . . . . . 98
value: 80h, 10000000b . . . . . . . . . . . . . . . . . . 59
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 59
XXh, XXXXXXXXb . . . . . . . . . . . . . . . . . . . . . . 60
40h, 01000000b . . . . . . . . . . . . . . . . . . . . . . . . 60
XXh, XXXXXXXXb . . . . . . . . . . . . . . . . . . . . . . 61
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 62
value: XXh, 00XXXXXXb . . . . . . . . . . . . . . . . . 63
value: XXh, 00XXXXXXb . . . . . . . . . . . . . . . . . 63
XXh, XXXXXXXXb . . . . . . . . . . . . . . . . . . . . . . 63
FFh, 11111111b . . . . . . . . . . . . . . . . . . . . . . . . 64
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . . 64
03h, 00000011b . . . . . . . . . . . . . . . . . . . . . . . . 64
interface types . . . . . . . . . . . . . . . . . . . . . . . . . 65
interface types . . . . . . . . . . . . . . . . . . . . . . . . . 65
pin TX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
pin TX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
(RFLevel amplifier deactivated) . . . . . . . . . . . . 83
Transmission module
© NXP B.V. 2011. All rights reserved.
PN512
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