HCPL-7800A Avago Technologies US Inc., HCPL-7800A Datasheet - Page 14

• Manufacturer Part Number: HCPL-7800A
• Description: Optocoupler
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-7800A

• No. Of Channels: 1
• Isolation Voltage: 3.75kV
• Optocoupler Output Type: Analog
• Input Current: 16mA
• Output Voltage: 3.8V
• Opto Case Style: DIP
• No. Of Pins: 8
• Peak Reflow Compatible (260 C): No
• Bandwidth: 100kHz
• Amplifier Type: Isolation
• Number Of Circuits: 1
• -3db Bandwidth: 100kHz
• Current - Input Bias: 500nA
• Voltage - Input Offset: 300µV
• Current - Supply: 10.9mA
• Current - Output / Channel: 16mA
• Voltage - Supply, Single/dual (±): 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• Slew Rate: -
• Gain Bandwidth Product: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 516-1141-5

As shown in Figure 18, 0.1 µF bypass capacitors (C1, C2)
should be located as close as possible to the pins of the
HCPL-7800(A). The bypass capacitors are required because
of the high-speed digital nature of the signals inside the
HCPL-7800(A). A 0.01 µF bypass capacitor (C2) is also rec-
ommended at the input due to the switched-capacitor
nature of the input circuit. The input bypass capacitor
also forms part of the anti-aliasing filter, which is recom-
mended to prevent high-frequency noise from aliasing
down to lower frequencies and interfering with the input
signal. The input filter also performs an important reliabil-
ity function—it reduces transient spikes from ESD events
flowing through the current sensing resistor.
Figure 18: Recommended Application Circuit.
Figure 19. Example Printed Circuit Board Layout.

* * *
TO R
TO R
SENSE+
SENSE-
MOTOR
TO V
DD1
+
R
SENSE
R5
-
HV+
HV-
C3
C1
0.1
µF
C2
* * *
GATE DRIVE
FLOATING
POSITIVE
CIRCUIT
SUPPLY
IN
78L05
C4
U1
OUT
R5
68
TO V
V
V
OUT+
OUT-
DD2
C2
0.1
µF
* * *
0.01
µF
C3
1
2
3
4
HCPL-7800
PC Board Layout
The design of the printed circuit board (PCB) should follow
good layout practices, such as keeping bypass capacitors
close to the supply pins, keeping output signals away
from input signals, the use of ground and power planes,
etc. In addition, the layout of the PCB can also affect the
isolation transient immunity (CMTI) of the HCPL-7800(A),
due primarily to stray capacitive coupling between the
input and the output circuits. To obtain optimal CMTI
performance, the layout of the PC board should minimize
any stray coupling by maintaining the maximum possible
distance between the input and output sides of the circuit
and ensuring that any ground or power plane on the PC
board does not pass directly below or extend much wider
than the body of the HCPL-7800(A).
U2
8
7
6
5
+5 V
C4
0.1 µF
150 pF
2.00 K
2.00 K
C6
R1
R2
R4
10.0 K
-
+
+15 V
-15 V
U3
150 pF
10.0 K
MC34081
C5
R3
0.1 µF
C7
0.1 µF
C8
V OUT