AFBR-53D5EZ Avago Technologies US Inc., AFBR-53D5EZ Datasheet - Page 9

• Manufacturer Part Number: AFBR-53D5EZ
• Description: Fiber Optic Transceiver,Module
• Manufacturer: Avago Technologies US Inc.

Specifications of AFBR-53D5EZ

• Wavelength: 860nm
• Applications: Ethernet
• Voltage - Supply: 4.75 V ~ 5.25 V
• Connector Type: SC
• Mounting Type: Through Hole
• Supply Voltage: 5.25V
• Wavelength Typ: 850nm
• Peak Reflow Compatible (260 C): Yes
• Leaded Process Compatible: No
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 516-1984

Table 1. Pinout Table
Figure 1. Transmitter Optical Eye Diagram Mask.

Pin
1
2
3
4
5
6
7
8
9
Mounting Pins
-0.2
1.3
1.0
0.8
0.5
0.2
0
0
0.22
Symbol
V
RD+
RD-
SD
V
V
TD-
TD+
V
EER
CCR
CCT
EET
NORMALIZED TIME
0.375
Functional Description
The mounting pins are provided for transceiver mechanical attachment to the circuit board.
They are embedded in the nonconductive plastic housing and are not connected to the trans-
ceiver internal circuit. They should be soldered into plated-through holes on the printed circuit
board.
Receiver Signal Ground
Directly connect this pin to receiver signal ground plane. (For AFBR-53D5Z, V
Receiver Data Out
RD+ is an open-emitter output circuit. Terminate this high-speed differential PECL output with
standard PECL techniques at the follow-on device input pin.
Receiver Data Out Bar
RD- is an open-emitter output circuit. Terminate this high-speed differential PECL output with
standard PECL techniques at the follow-on device input pin.
Signal Detect
Normal optical input levels to the receiver result in a logic “1” output, V
optical levels to the receiver result in a fault condition indicated by a logic “0” output V
deasserted.
Signal Detect is a single-ended PECL output. SD can be terminated with standard PECL tech-
niques via 50 W to V
conserve electrical power with small compromise to signal quality. If Signal Detect output is
not used, leave it open-circuited. This Signal Detect output can be used to drive a PECL input
on an upstream circuit, such as, Signal Detect input pr Loss of Signal-bar.
Receiver Power Supply
Provide +5 Vdc via the recommended receiver power supply filter circuit.
Locate the power supply filter circuit as close as possible to the V
Transmitter Power Supply
Provide +5 Vdc via the recommended transmitter power supply filter circuit.
Locate the power supply filter circuit as close as possible to the V
Transmitter Data In-Bar
Terminate this high-speed differential PECL input with standard PECL techniques at the trans-
mitter input pin.
Transmitter Data In
Terminate this high-speed differential PECL input with standard PECL techniques at the trans-
mitter input pin.
Transmitter Signal Ground
Directly connect this pin to the transmitter signal ground plane.
0.625
0.78
1.0
CCR
- 2V. Alternatively, SD can be loaded with a 270W resistor to V
Figure 2. Pin-Out.
NIC = NO INTERNAL CONNECTION (MOUNTING PINS)
1 = V
2 = RD+
3 = RD-
4 = SD
5 = V
6 = V
7 = TD-
8 = TD+
9 = V
EER
CCR
CCT
EET
TOP VIEW
NIC
NIC
CCR
CCT
pin.
pin.
OH
RX
TX
, asserted. Low input
EER =
V
EET
EER
OH
)
to
,