PIC18F2520T-I/ML Microchip Technology, PIC18F2520T-I/ML Datasheet - Page 171

• Manufacturer Part Number: PIC18F2520T-I/ML
• Description: 28 PIN, 32 KB ENHFLASH, 1.5 KB RAM, 25 I/O PB FREE,
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2520T-I/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCP3909RD-3PH1 - REF DESIGN MCP3909 3PH ENGY MTR
• Lead Free Status / Rohs Status: Details

17.3.8
In SPI Master mode, module clocks may be operating
at a different speed than when in full-power mode; in
the case of Sleep mode, all clocks are halted.
In most Idle modes, a clock is provided to the peripher-
als. That clock should be from the primary clock
source, the secondary clock (Timer1 oscillator at
32.768 kHz) or the INTOSC source. See Section 2.7
“Clock Sources and Oscillator Switching” for
additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the con-
troller from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all 8 bits have been
received, the MSSP interrupt flag bit will be set, and if
enabled, will wake the device.
TABLE 17-2:
© 2008 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISA
TRISC
SSPBUF
SSPCON1
SSPSTAT
Legend: Shaded cells are not used by the MSSP in SPI mode.
Note 1:
Name
2:
These bits are unimplemented in 28-pin devices; always maintain these bits clear.
PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
OPERATION IN POWER-MANAGED
MODES
PORTC Data Direction Register
MSSP Receive Buffer/Transmit Register
TRISA7
GIE/GIEH PEIE/GIEL TMR0IE
PSPIE
PSPIP
PSPIF
WCOL
Bit 7
SMP
REGISTERS ASSOCIATED WITH SPI OPERATION
(1)
(1)
(1)
(2)
TRISA6
SSPOV
ADIE
ADIP
Bit 6
ADIF
CKE
(2)
PORTA Data Direction Register
SSPEN
RCIE
RCIP
RCIF
Bit 5
D/A
PIC18F2420/2520/4420/4520
INT0IE
TXIE
TXIP
Bit 4
TXIF
CKP
P
SSPM3
SSPIE
SSPIP
SSPIF
17.3.9
A Reset disables the MSSP module and terminates the
current transfer.
17.3.10
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1:
There is also an SMP bit which controls when the data
is sampled.
RBIE
Bit 3
Standard SPI Mode
S
Terminology
0, 0
0, 1
1, 0
1, 1
TMR0IF
CCP1IF
CCP1IE
CCP1IP
SSPM2
EFFECTS OF A RESET
BUS MODE COMPATIBILITY
Bit 2
R/W
SPI BUS MODES
TMR2IF
TMR2IE
TMR2IP
SSPM1
INT0IF
Bit 1
UA
CKP
Control Bits State
0
0
1
1
TMR1IF
TMR1IE
TMR1IP
SSPM0
RBIF
Bit 0
DS39631E-page 169
BF
CKE
on page
Values
Reset
1
0
1
0
49
52
52
52
52
52
50
50
50