PIC18F2420-E/SP Microchip Technology, PIC18F2420-E/SP Datasheet - Page 266
PIC18F2420-E/SP
Manufacturer Part Number
PIC18F2420-E/SP
Description
28 PIN, 16 KB STD FLASH, 3804 RAM, 25 I/O, PB FREE,
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2420-IML.pdf
(412 pages)
2.PIC18F2420-IML.pdf
(16 pages)
3.PIC18F2420-IML.pdf
(8 pages)
4.PIC18F2420-IML.pdf
(6 pages)
5.PIC18F2420-IML.pdf
(8 pages)
6.PIC18F2420-IML.pdf
(4 pages)
Specifications of PIC18F2420-E/SP
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2420-E/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2420-IML PDF datasheet
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- PIC18F2420-IML PDF datasheet #3
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- PIC18F2420-IML PDF datasheet #5
- PIC18F2420-IML PDF datasheet #6
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- Download datasheet (7Mb)
PIC18F2420/2520/4420/4520
23.5.1
The program memory may be read to, or written from,
any location using the table read and table write
instructions. The Device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A block
of user memory may be protected from table writes if the
WRTn Configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the EBTRn
bit set to ‘0’, a table read instruction that executes from
within that block is allowed to read. A table read
FIGURE 23-6:
DS39631E-page 264
TBLPTR = 0008FFh
Results: All table writes disabled to Blockn whenever WRTn = 0
Register Values
PROGRAM MEMORY
CODE PROTECTION
PC = 001FFEh
PC = 005FFEh
TABLE WRITE (WRTn) DISALLOWED
Program Memory
TBLWT*
TBLWT*
instruction that executes from a location outside of that
block is not allowed to read and will result in reading ‘0’s.
Figures 23-6 through 23-8 illustrate table write and table
read protection.
Note:
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
.
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code pro-
tection bits are only set to ‘1’ by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP or an external
programmer.
Configuration Bit Settings
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
© 2008 Microchip Technology Inc.
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