DSPIC30F6010-20E/PF Microchip Technology, DSPIC30F6010-20E/PF Datasheet - Page 3

• Manufacturer Part Number: DSPIC30F6010-20E/PF
• Description: IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010-20E/PF

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TQFP, 80-VQFP
• Package: 80TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F601020EPF

34. Timer Module
35. PLL Lock Status Bit
36. PSV Operations
37. I
38. I
39. I
The following sections describe the errata and work
around to these errata, where they may apply.
© 2008 Microchip Technology Inc.
Clock switching prevents the device from waking
up from Sleep.
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register on address match if the
Least Significant bits of the address are the same
as the 7-bit reserved addresses.
When the I
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02.
When the I
device generates a glitch on the SDA and SCL
pins, causing a false communication start in a
single-master configuration or a bus collision in a
multi-master configuration.
2
2
2
C Module: 10-bit Addressing Mode
C Module: 10-bit Addressing Mode
C Module
2
C module is enabled, the dsPIC
2
C module is configured as a 10-bit
®
DSC
1. Module: Data EEPROM – Speed
2. Module: CPU – Unsigned
At device throughput is greater than 20 MIPS for
V
V
instructions (TBLRDL/TBLRDH) and instructions
that use PSV do not function correctly when
reading data from Data EEPROM.
Work around
When reading data from Data EEPROM, the
application
operation to lower the frequency of the system
clock so that the throughput is less than 20 MIPS.
This may be easily performed at any time via the
Oscillator
(OSCCON<7:6>), that allow the application to
divide the system clock down by a factor of 4, 16
or 64.
The US (CORCON<12>) bit controls whether
MAC-type DSP instructions operate in Signed or
Unsigned mode. The device defaults to a Signed
mode on power-up (US = 0).
For this revision of silicon, MAC-type DSP
instructions do not function as specified in
Unsigned mode (US = 1). Also, for this revision,
the US bit will always read as ‘0’.
Work around
Ensure that the US bit is not set by the application.
In
multiplications, use the MCU Multiply instruction,
MUL.UU.
DD
DD
in the range 4.75V to 5.5V (or 10 MIPS for
order
in the range 3V to 3.6V), Table Read
dsPIC30F6010
should
to
Postscaler
perform
perform
unsigned
MAC
bits,
DS80195H-page 3
a
clock-switch
integer
POST