TC500ACPE TELCOM SEMICONDUCTOR, TC500ACPE Datasheet - Page 7

• Manufacturer Part Number: TC500ACPE
• Description: IC, ANALOGUE PROCESSOR, DIP16, 500
• Manufacturer: TELCOM SEMICONDUCTOR

Specifications of TC500ACPE

• Brief Features: Low Power Dissipation, Automatic Input Voltage Polarity Detection
• Supply Voltage Range: 4.5V To 7.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: DIP
• No. Of: RoHS Compliant
• Ic Function: Precision Analogue Front Ends
• Rohs Compliant: Yes

4.0
4.1
Actual data conversion is accomplished in two phases:
input signal integration and reference voltage de-
integration.
The integrator output is initialized to 0V prior to the start
of integration. During integration, analog switch S
nects V
for a fixed time period (T
causes the integrator output to depart 0V at a rate deter-
mined by the magnitude of V
mined by the polarity of V
initiated immediately at the expiration of T
During de-integration, S1 connects a reference voltage
(having a polarity opposite that of V
input. At the same time, an external precision timer is
started. The de-integration phase is maintained until
the comparator output changes state, indicating the
integrator has returned to its starting point of 0V. When
this occurs, the precision timer is stopped. The de-
integration time period (T
precision timer, is directly proportional to the magnitude
of the applied input voltage (see Figure 4-3).
A simple mathematical equation relates the input
signal, reference voltage and integration time:
EQUATION 4-1:
For a constant V
EQUATION 4-2:
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as
they are stable during a measurement cycle.
An inherent benefit is noise immunity. Input noise
spikes are integrated (averaged to zero) during the
integration periods. Integrating ADCs are immune to
the large conversion errors that plague successive
approximation converters in high noise environments.
Integrating converters provide inherent noise rejection
with at least a 20dB/decade attenuation rate.
Interference signals with frequencies at integral
 2004 Microchip Technology Inc.
Where:
V
T
t
DEINT
INT
REF
= Signal Integration time (fixed)
= Reference Voltage
----------------------- -
R
= Reference Voltage Integration time (variable)
IN
INT
DETAILED DESCRIPTION
Dual Slope Conversion Principles
to the integrator input where it is maintained
1
C
INT
IN
∫
T
0
V
:
INT
IN
V
=
IN
V
IN
T DT
DEINT
REF
INT
. The de-integration phase is
). The application of V
IN
T
----------------- -
DEINT
T
), as measured by the
=
INT
and a direction deter-
V
------------------------------- -
IN
REF
R
) to the integrator
INT
C
C
INT
DEINT
INT
.
1
con-
IN
multiples of the integration period are, theoretically,
completely removed, since the average value of a sine
wave of frequency (1/T) averaged over a period (T) is
zero.
Integrating converters often establish the integration
period to reject 50/60 Hz line frequency interference
signals. The ability to reject such signals is shown by a
normal mode rejection plot (Figure 4-1). Normal mode
rejection is limited in practice to 50 to 65 dB, since the
line frequency can deviate by a few tenths of a percent
(Figure 4-2).
FIGURE 4-1:
Normal Mode Rejection.
FIGURE 4-2:
30
20
10
0.1/T
0
Line Frequency Deviation from 60 Hz (%)
80
70
60
50
40
30
20
T = Measurment
0.01
TC500/A/510/514
Normal Mode
DEV = Deviation from 60 Hz
t = Integration Period
REJECTION
Period
Input Frequency
Integrating Converter
Line Frequency Deviation.
= 20 LOG
0.1
1/T
t = 0.1 sec
SIN 60 t (1 ±
60 t (1 ±
p
p
DS21428C-page 7
DEV
DEV
100
100
)
)
1.0
10/T