DSPIC30F4011-20E/P Microchip Technology, DSPIC30F4011-20E/P Datasheet - Page 18

• Manufacturer Part Number: DSPIC30F4011-20E/P
• Description: IC, DSC, 16BIT, 48KB, 40MHZ, 5.5V, DIP40
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F4011-20E/P

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F003 - MODULE SOCKET DSPIC30F 40DIPACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: DSPIC30F4011-20EP

dsPIC30F4011/4012
27. Module: OSC2 Pin
28. Module: CAN
29. Module: CAN
DS80454D-page 18
The port pin, RC15, is multiplexed with the primary
oscillator pin, OSC2. When pin RC15 is required
for digital input/output, specific bits in the Oscillator
Configuration register, FOSC, may be set up as
follows:
• FOS<2:0> bits (FOSC<10:8>) configured for
• FPR<4:0> bits (FOSC<4:0>) may be
For this revision of silicon, if the RC15 digital I/O
port function is desired, the FPR<4:0> bits in the
FOSC Configuration register may not be set up for
FRC w/PLL 4x/8x/16x modes.
Work around
None.
In future revisions of silicon, port pin RC15 may
also be configured for digital I/O when the
FPR<4:0> bits in the FOSC Configuration register
are set up for FRC w/PLL 4x/8x/16x modes.
Affected Silicon Revisions
CAN Receive filters 3, 4 and 5 may not work for a
given combination of instruction cycle speed and
CAN bit time quanta.
Work around
Do not use CAN RX filters 3, 4 and 5. Instead,
use filters 0, 1 and 2.
Affected Silicon Revisions
The C1EC register does not reflect the correct
error count value. The error flags in the C1INTF
register are updated correctly and can be read
correctly.
Work around
Do not use the C1EC register for error manage-
ment. Use the error state flags in the C1INTF
register instead.
Affected Silicon Revisions
A1
A1
A1
LP, LPRC, FRC, ECIO, ERCIO or ECIO
w/PLL 4x/8x/16x
configured for ECIO w/PLL 4x/8x/16x
X
X
X
A2
A2
A2
X
X
A3
A3
A3
X
X
A4
A4
A4
X
X
30. Module: QEI
31. Module: QEI
32. Module: ADC
When the TQCS and TQGATE bits in the
QEIxCON register are set, a QEI interrupt
should be generated after an input pulse on the
QEA input. This interrupt is not generated in the
affected silicon.
Work around
None.
Affected Silicon Revisions
When the TQCS and TQGATE bits in the QEIx-
CON register are set, the POSCNT counter
should not increment but erroneously does, and
if allowed to increment to match MAXCNT, a QEI
interrupt will be generated.
Work around
To
POSCNT while running the QEI in Timer Gated
Accumulation mode, initialize MAXCNT = 0.
Affected Silicon Revisions
If the ADC module is in an enabled state when the
device enters Sleep mode as a result of executing
a PWRSAV #0 instruction, the device power-down
current (I
in the device data sheet. This may happen even if
the ADC module is disabled by clearing the ADON
bit prior to entering Sleep mode.
Work around
In order to remain within the I
listed in the device data sheet, the user software
must completely disable the ADC module by
setting the ADC Module Disable bit in the
corresponding
(PMDx) register, prior to executing a PWRSAV
#0 instruction.
Affected Silicon Revisions
A1
A1
A1
X
X
X
prevent
A2
A2
A2
X
X
X
PD
) may exceed the specifications listed
A3
A3
A3
X
the erroneous
X
X
Peripheral
© 2010 Microchip Technology Inc.
A4
A4
A4
X
X
X
Module
PD
increment
specifications
Disable
of