FT232RQ FTDI, FT232RQ Datasheet - Page 5

• Manufacturer Part Number: FT232RQ
• Description: IC, USB UART INTERFACE, QFN-32
• Manufacturer: FTDI

Specifications of FT232RQ

• Supply Voltage Range: 1.8V To 5.25V, 3.3V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 32
• Termination Type: SMD
• Bandwidth: 48MHz
• Ic Generic Number: 232
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3. Block Diagram
3.1 Block Diagram (Simplified)
Figure 1 - FT232R Block Diagram
3.3V LDO Regulator - The 3.3V LDO Regulator generates the 3.3V reference voltage for driving the USB transceiver
cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It
also provides 3.3V power to the 1.5kΩ internal pull up resistor on USBDP. The main function of this block is to power
the USB Transceiver and the Reset Generator Cells rather than to power external logic. However, external circuitry
requiring a 3.3V nominal supply at a current of around than 50mA could also draw its power from the 3V3OUT pin, if
required.
USB Transceiver - The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB
cable. The output drivers provide 3.3V level slew rate control signalling, whilst a differential receiver and two single
ended receivers provide USB data in, SEO and USB Reset condition detection. This Cell also incorporates internal
USB series resistors on the USB data lines, and a 1.5kΩ pull up resistor on USBDP.
USB DPLL - The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and
data signals to the SIE block.
Internal 12MHz Oscillator - The Internal 12MHz Oscillator cell generates a 12MHz reference clock input to the x4
Clock multiplier. The 12MHz Oscillator is also used as the reference clock for the SIE, USB Protocol Engine and
UART FIFO controller blocks
Clock Multiplier / Divider - The Clock Multiplier / Divider takes the 12MHz input from the Oscillator Cell and
generates the 48MHz, 24MHz, 12MHz, and 6MHz reference clock signals. The 48Mz clock reference is used for the
USB DPLL and the Baud Rate Generator blocks.
FT232R USB UART I.C. Datasheet Version 1.04
3V3OUT
(optional)
(optional)
USBDM
USBDP
VCC
OSCO
OCSI
TEST
GND
3.2 Functional Block Descriptions
Transceiver
Integrated
Resistors
USB DPLL
Regulator
Oscillator
and 1.5K
Pull-up
Internal
3.3 Volt
Series
12MHz
USB
with
LDO
Multiplier /
Serial Interface
Divider
Clock
Engine
( SIE )
Transceiver
48MHz
To USB
24 MHz
12 MHz
Cell
6 MHz
Protocol Engine
FIFO RX Buffer
FIFO TX Buffer
128 bytes
256 bytes
EEPROM
Internal
USB
To USB Transceiver Cell
RESET#
FIFO Controller
© Future Technology Devices International Ltd. 2005
UART
48MHz
VCCIO
GENERATOR
3V3OUT
RESET
UART Controller
Signal Inversion
Programmable
and High Drive
Baud Rate
Generator
with
TXD
RXD
RTS#
CTS#
DTR#
DSR#
DCD#
RI#
CBUS0
CBUS1
CBUS2
CBUS3
CBUS4