SC16C652BIB48 NXP Semiconductors, SC16C652BIB48 Datasheet - Page 9

• Manufacturer Part Number: SC16C652BIB48
• Description: IC, UART, DUAL, 32BYTE FIFO, 16C652
• Manufacturer: NXP Semiconductors

Specifications of SC16C652BIB48

• No. Of Channels: 2
• Data Rate: 5Mbps
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Uart Features: Independent Transmit & Receive UART Control, Software Selectable Baud Rate Generator
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
SC16C652B_4
Product data sheet
6.3 FIFO operation
6.4 Hardware flow control
6.5 Software flow control
The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
bit 0 (FCR[0]). With 16C2550 devices, the user can set the receive trigger level, but not
the transmit trigger level. The SC16C652B provides independent trigger levels for both
receiver and transmitter. To remain compatible with SC16C2550, the transmit interrupt
trigger level is set to 16 following a reset. It should be noted that the user can set the
transmit trigger levels by writing to the FCR, but activation will not take place until EFR[4]
is set to a logic 1. The receiver FIFO section includes a time-out function to ensure data is
delivered to the external CPU. An interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the loading of a character or the receive
trigger level has not been reached.
Table 5:
When automatic hardware flow control is enabled, the SC16C652B monitors the CTS pin
for a remote buffer overflow indication and controls the RTS pin for local buffer overflows.
Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to
a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a flow control request,
ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C652B will suspend
TX transmissions as soon as the stop bit of the character in process is shifted out.
Transmission is resumed after the CTS input returns to a logic 0, indicating more data may
be sent.
With the Auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1 (RTS
off), until the receive FIFO reaches the next trigger level. However, the RTS pin will return
to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the
programmed trigger level. However, under the above described conditions, the
SC16C652B will continue to accept data until the receive FIFO is full.
When software flow control is enabled, the SC16C652B compares one or two sequential
receive data characters with the programmed Xon or Xoff character value(s). If received
character(s) match the programmed Xoff values, the SC16C652B will halt transmission
(TX) as soon as the current character(s) has completed transmission. When a match
occurs, the receive ready (if enabled via Xoff IER[5]) flags will be set and the interrupt
output pin (if receive interrupt is enabled) will be activated. Following a suspension due to
a match of the Xoff characters’ values, the SC16C652B will monitor the receive data
stream for a match to the Xon1/Xon2 character value(s). If a match is found, the
SC16C652B will resume operation and clear the flags (ISR[4]).
Selected trigger level
(characters)
8
16
24
28
Flow control mechanism
Rev. 04 — 1 September 2005
INT pin activation
RX
8
16
24
28
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
TX
16
8
24
30
Negate RTS or
send Xoff
8
16
24
28
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC16C652B
Assert RTS or
send Xon
0
7
15
23
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