LTC485IN8.#PBF Linear Technology, LTC485IN8.#PBF Datasheet - Page 7

• Manufacturer Part Number: LTC485IN8.#PBF
• Description: IC, TRANSCEIVER RS485, DIP8, 485
• Manufacturer: Linear Technology

Specifications of LTC485IN8.#PBF

• Device Type: Differential
• No. Of Drivers: 1
• Supply Voltage Range: 4.75V To 5.25V
• Driver Case Style: DIP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Interface Type: RS422, RS485
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
Basic Theory of Operation
Previous RS485 transceivers have been designed using
bipolar technology because the common-mode range of
the device must extend beyond the supplies and the device
must be immune to ESD damage and latchup. Unfortu-
nately, the bipolar devices draw a large amount of supply
current, which is unacceptable for the numerous applica-
tions that require low power consumption. The LTC485 is
the first CMOS RS485/RS422 transceiver which features
ultra-low power consumption without sacrificing ESD and
latchup immunity.
The LTC485 uses a proprietary driver output stage, which
allows a common-mode range that extends beyond the
power supplies while virtually eliminating latchup and
providing excellent ESD protection. Figure 9 shows the
LTC485 output stage while Figure 10 shows a conven-
tional CMOS output stage.
When the conventional CMOS output stage of Figure 10
enters a high impedance state, both the P-channel (P1)
and the N-channel (N1) are turned off. If the output is then
driven above V
Figure 9. LTC485 Output Stage
CC
LOGIC
or below ground, the P + /N-well diode
U U
N1
P1
V
CC
SD4
SD3
LTC485 • F09
OUTPUT
W
D1
D2
U
(D1) or the N + /P-substrate diode (D2) respectively will
turn on and clamp the output to the supply. Thus, the
output stage is no longer in a high impedance state and is
not able to meet the RS485 common-mode range require-
ment. In addition, the large amount of current flowing
through either diode will induce the well known CMOS
latchup condition, which could destroy the device.
The LTC485 output stage of Figure 9 eliminates these
problems by adding two Schottky diodes, SD3 and SD4.
The Schottky diodes are fabricated by a proprietary modi-
fication to the standard N-well CMOS process. When the
output stage is operating normally, the Schottky diodes
are forward biased and have a small voltage drop across
them. When the output is in the high impedance state and
is driven above V
D1 or D2 still turn on, but SD3 or SD4 will reverse bias and
prevent current from flowing into the N-well or the sub-
strate. Thus, the high impedance state is maintained even
with the output voltage beyond the supplies. With no
minority carrier current flowing into the N-well or sub-
strate, latchup is virtually eliminated under power-up or
power-down conditions.
Figure 10. Conventional CMOS Output Stage
LOGIC
CC
or below ground, the parasitic diodes
N1
P1
V
CC
LTC485 • F10
OUTPUT
D1
D2
LTC485
LTC485ff
7